[Mesa-dev] [PATCH] nir: call nir_index_local_regs(..) to update reg_alloc
Christian Gmeiner
christian.gmeiner at gmail.com
Sun Jun 24 21:28:44 UTC 2018
Hi Jason
Am So., 24. Juni 2018 um 22:14 Uhr schrieb Jason Ekstrand
<jason at jlekstrand.net>:
>
> In general, drivers and passes shouldn't rely on the results of
> index_*_regs or index_ssa_defs after an optimization or lowering pass is
> run. We've considered the results of those functions to be too volatile to
> try and keep up to date. Drivers or passes are expected to call the
> indexing function themselves if they need that information.
>
Ah good to know.. and I think that's the route I will choose.
>
> That doesn't mean this change is necessarily wrong or that we don't want to
> move in a direction of trying to keep more of that information up to date.
> It does mean that the behavior you're seeing isn't really a bug and that
> changing that behavior will require more than just this patch. Could you
> provide more context on what issue you're having and what you're trying to
> accomplish?
>
I want to go the simplest route for backend ir and register allocation :)
Lets start with this simple nir shader:
shader: MESA_SHADER_FRAGMENT
inputs: 2
outputs: 1
uniforms: 0
shared: 0
decl_var shader_in INTERP_MODE_SMOOTH vec4 in_0 (VARYING_SLOT_VAR20, 0, 0)
decl_var shader_in INTERP_MODE_SMOOTH vec4 in_1 (VARYING_SLOT_VAR21, 1, 0)
decl_var shader_out INTERP_MODE_NONE vec4 out_0 (FRAG_RESULT_COLOR, 0, 0)
decl_function main returning void
impl main {
decl_reg vec4 32 r0
decl_reg vec4 32 r1
block block_0:
/* preds: */
vec1 32 ssa_0 = load_const (0x00000000 /* 0.000000 */)
vec4 32 ssa_1 = intrinsic load_input (ssa_0) () (1, 0) /*
base=1 */ /* component=0 */ /* in_1 */
vec4 32 ssa_2 = fmov ssa_1.xyyy
r1.xy = fmov ssa_2.xy
vec4 32 ssa_3 = fmov r1
vec2 32 ssa_4 = imov ssa_3.xy
vec4 32 ssa_5 = tex ssa_4 (coord), 0 (texture) 0 (sampler)
r1 = imov ssa_5
vec4 32 ssa_6 = fmov r1
vec1 32 ssa_7 = load_const (0x00000000 /* 0.000000 */)
vec4 32 ssa_8 = intrinsic load_input (ssa_7) () (0, 0) /*
base=0 */ /* component=0 */ /* in_0 */
vec4 32 ssa_9 = fmov ssa_8
r1 = fmul ssa_6, ssa_9
vec4 32 ssa_10 = fmov r1
r0 = fmov ssa_10
vec1 32 ssa_11 = load_const (0x00000000 /* 0.000000 */)
intrinsic store_output (r0, ssa_11) () (0, 15, 0) /* base=0 */
/* wrmask=xyzw */ /* component=0 */ /* out_0 */
/* succs: block_0 */
block block_0:
}
Which gets transformed to this:
shader: MESA_SHADER_FRAGMENT
inputs: 2
outputs: 1
uniforms: 0
shared: 0
decl_var shader_in INTERP_MODE_SMOOTH vec4 in_0 (VARYING_SLOT_VAR20, 0, 0)
decl_var shader_in INTERP_MODE_SMOOTH vec4 in_1 (VARYING_SLOT_VAR21, 1, 0)
decl_var shader_out INTERP_MODE_NONE vec4 out_0 (FRAG_RESULT_COLOR, 0, 0)
decl_function main returning void
impl main {
block block_0:
/* preds: */
vec1 32 ssa_0 = load_const (0x00000000 /* 0.000000 */)
vec4 32 ssa_1 = intrinsic load_input (ssa_0) () (1, 0) /*
base=1 */ /* component=0 */ /* in_1 */
vec2 32 ssa_2 = imov ssa_1.xy
vec4 32 ssa_3 = tex ssa_2 (coord), 0 (texture) 0 (sampler)
vec4 32 ssa_4 = intrinsic load_input (ssa_0) () (0, 0) /*
base=0 */ /* component=0 */ /* in_0 */
vec4 32 ssa_5 = fmul ssa_3, ssa_4
intrinsic store_output (ssa_5, ssa_0) () (0, 15, 0) /* base=0
*/ /* wrmask=xyzw */ /* component=0 */ /* out_0 */
/* succs: block_0 */
block block_0:
}
After using nir_convert_from_ssa(..) I get this:
shader: MESA_SHADER_FRAGMENT
inputs: 2
outputs: 1
uniforms: 0
shared: 0
decl_var shader_in INTERP_MODE_SMOOTH vec4 in_0 (VARYING_SLOT_VAR20, 0, 0)
decl_var shader_in INTERP_MODE_SMOOTH vec4 in_1 (VARYING_SLOT_VAR21, 1, 0)
decl_var shader_out INTERP_MODE_NONE vec4 out_0 (FRAG_RESULT_COLOR, 0, 0)
decl_function main returning void
impl main {
decl_reg vec4 32 r2
decl_reg vec2 32 r3
decl_reg vec4 32 r4
decl_reg vec4 32 r5
decl_reg vec4 32 r6
block block_0:
/* preds: */
vec1 32 ssa_0 = load_const (0x00000000 /* 0.000000 */)
r2 = intrinsic load_input (ssa_0) () (1, 0) /* base=1 */ /*
component=0 */ /* in_1 */
r3 = imov r2.xy
r4 = tex r3 (coord), 0 (texture) 0 (sampler)
r5 = intrinsic load_input (ssa_0) () (0, 0) /* base=0 */ /*
component=0 */ /* in_0 */
r6 = fmul r4, r5
intrinsic store_output (r6, ssa_0) () (0, 15, 0) /* base=0 */
/* wrmask=xyzw */ /* component=0 */ /* out_0 */
/* succs: block_0 */
block block_0:
}
~ at this point I convert nir to my backend ir where I am using the
register indexes as they are for live tracking and register
allocation and there I run into some troubles with not used r0 and r1.
I thought that I should fix this 'problem' at the core directly
at nir level, but I am happy to do the nir_index_local_regs thing in
the backend.
>
> --Jason
>
>
> On June 24, 2018 09:37:05 Christian Gmeiner <christian.gmeiner at gmail.com>
> wrote:
>
> > After calling nir_lower_regs_to_ssa(..) nir_function_impl's reg_alloc
> > counter still hold its old value. Just call nir_index_local_regs(..) to
> > set reg_alloc to the correct value - which should be 0.
> >
> > Signed-off-by: Christian Gmeiner <christian.gmeiner at gmail.com>
> > ---
> > src/compiler/nir/nir_lower_regs_to_ssa.c | 2 ++
> > 1 file changed, 2 insertions(+)
> >
> > diff --git a/src/compiler/nir/nir_lower_regs_to_ssa.c
> > b/src/compiler/nir/nir_lower_regs_to_ssa.c
> > index d70e70260b..7214e92b90 100644
> > --- a/src/compiler/nir/nir_lower_regs_to_ssa.c
> > +++ b/src/compiler/nir/nir_lower_regs_to_ssa.c
> > @@ -275,6 +275,8 @@ nir_lower_regs_to_ssa_impl(nir_function_impl *impl)
> > }
> > }
> >
> > + nir_index_local_regs(impl);
> > +
> > free(state.values);
> >
> > nir_metadata_preserve(impl, nir_metadata_block_index |
> > --
> > 2.17.1
> >
> > _______________________________________________
> > mesa-dev mailing list
> > mesa-dev at lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/mesa-dev
>
>
>
--
greets
--
Christian Gmeiner, MSc
https://christian-gmeiner.info
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