[Mesa-dev] [PATCH 07/12] intel/compiler: More peephole select

[Ian Romanick]

From: Ian Romanick <ian.d.romanick at intel.com>

Shader-db results:

The one shader hurt for instructions is a compute shader that had both
spills and fills hurt.  The other shader that had spill hurt also had
fills helped by more.

Skylake, Broadwell, and Haswell had similar results. (Skylake shown)
total instructions in shared programs: 14371513 -> 14346174 (-0.18%)
instructions in affected programs: 890389 -> 865050 (-2.85%)
helped: 3601
HURT: 1
helped stats (abs) min: 1 max: 92 x̄: 7.05 x̃: 4
helped stats (rel) min: 0.10% max: 25.00% x̄: 3.95% x̃: 3.23%
HURT stats (abs)   min: 43 max: 43 x̄: 43.00 x̃: 43
HURT stats (rel)   min: 0.90% max: 0.90% x̄: 0.90% x̃: 0.90%
95% mean confidence interval for instructions value: -7.27 -6.80
95% mean confidence interval for instructions %-change: -4.05% -3.84%
Instructions are helped.

total cycles in shared programs: 532435951 -> 532154282 (-0.05%)
cycles in affected programs: 69203137 -> 68921468 (-0.41%)
helped: 2654
HURT: 981
helped stats (abs) min: 1 max: 4496 x̄: 177.17 x̃: 76
helped stats (rel) min: <.01% max: 71.34% x̄: 9.16% x̃: 5.42%
HURT stats (abs)   min: 1 max: 33338 x̄: 192.20 x̃: 19
HURT stats (rel)   min: <.01% max: 36.36% x̄: 2.95% x̃: 1.46%
95% mean confidence interval for cycles value: -113.38 -41.60
95% mean confidence interval for cycles %-change: -6.24% -5.53%
Cycles are helped.

total spills in shared programs: 8114 -> 8122 (0.10%)
spills in affected programs: 152 -> 160 (5.26%)
helped: 0
HURT: 2

total fills in shared programs: 11082 -> 11100 (0.16%)
fills in affected programs: 375 -> 393 (4.80%)
helped: 1
HURT: 1

Ivy Bridge
total instructions in shared programs: 11674299 -> 11643589 (-0.26%)
instructions in affected programs: 897238 -> 866528 (-3.42%)
helped: 3312
HURT: 18
helped stats (abs) min: 1 max: 99 x̄: 9.32 x̃: 6
helped stats (rel) min: 0.11% max: 31.18% x̄: 5.21% x̃: 3.36%
HURT stats (abs)   min: 2 max: 20 x̄: 7.89 x̃: 6
HURT stats (rel)   min: 0.70% max: 2.59% x̄: 1.63% x̃: 1.70%
95% mean confidence interval for instructions value: -9.51 -8.93
95% mean confidence interval for instructions %-change: -5.34% -5.00%
Instructions are helped.

total cycles in shared programs: 256268731 -> 255798436 (-0.18%)
cycles in affected programs: 69839413 -> 69369118 (-0.67%)
helped: 2727
HURT: 626
helped stats (abs) min: 1 max: 12850 x̄: 211.76 x̃: 90
helped stats (rel) min: <.01% max: 75.90% x̄: 9.75% x̃: 6.40%
HURT stats (abs)   min: 1 max: 30855 x̄: 171.18 x̃: 10
HURT stats (rel)   min: <.01% max: 36.36% x̄: 2.86% x̃: 0.59%
95% mean confidence interval for cycles value: -164.62 -115.90
95% mean confidence interval for cycles %-change: -7.76% -7.03%
Cycles are helped.

total spills in shared programs: 4544 -> 4532 (-0.26%)
spills in affected programs: 173 -> 161 (-6.94%)
helped: 3
HURT: 0

total fills in shared programs: 4831 -> 4822 (-0.19%)
fills in affected programs: 250 -> 241 (-3.60%)
helped: 3
HURT: 0

Sandy Bridge
total instructions in shared programs: 10423753 -> 10415101 (-0.08%)
instructions in affected programs: 221138 -> 212486 (-3.91%)
helped: 775
HURT: 0
helped stats (abs) min: 1 max: 88 x̄: 11.16 x̃: 8
helped stats (rel) min: 0.11% max: 23.08% x̄: 4.87% x̃: 3.48%
95% mean confidence interval for instructions value: -12.11 -10.22
95% mean confidence interval for instructions %-change: -5.18% -4.55%
Instructions are helped.

total cycles in shared programs: 146097855 -> 145978888 (-0.08%)
cycles in affected programs: 3837129 -> 3718162 (-3.10%)
helped: 548
HURT: 273
helped stats (abs) min: 1 max: 2670 x̄: 240.55 x̃: 60
helped stats (rel) min: 0.04% max: 39.18% x̄: 4.23% x̃: 1.72%
HURT stats (abs)   min: 1 max: 1976 x̄: 47.08 x̃: 10
HURT stats (rel)   min: <.01% max: 67.72% x̄: 2.84% x̃: 0.62%
95% mean confidence interval for cycles value: -173.18 -116.63
95% mean confidence interval for cycles %-change: -2.36% -1.40%
Cycles are helped.

No change on Iron Lake or GM45.

Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
---
 src/intel/compiler/brw_nir.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c
index 67c062d91f5..6a0d4090fa7 100644
--- a/src/intel/compiler/brw_nir.c
+++ b/src/intel/compiler/brw_nir.c
@@ -557,7 +557,22 @@ brw_nir_optimize(nir_shader *nir, const struct brw_compiler *compiler,
       OPT(nir_copy_prop);
       OPT(nir_opt_dce);
       OPT(nir_opt_cse);
+
+      /* Passing 0 to the peephole select pass causes it to convert
+       * if-statements that contain only move instructions in the branches
+       * regardless of the count.
+       *
+       * Passing 0 to the peephole select pass causes it to convert
+       * if-statements that contain at most a single ALU instruction (total)
+       * in both branches.  Before Gen6, some math instructions were
+       * prohibitively expensive and the results of compare operations need an
+       * extra resolve step.  For these reasons, this pass is more harmful
+       * than good on those platforms.
+       */
       OPT(nir_opt_peephole_select, 0);
+      if (compiler->devinfo->gen >= 6)
+         OPT(nir_opt_peephole_select, 1);
+
       OPT(nir_opt_intrinsics);
       OPT(nir_opt_algebraic);
       OPT(nir_opt_constant_folding);
-- 
2.14.4