[Mesa-dev] [PATCH 1/3] radeonsi: move VS_STATE_SGPR before draw SGPRs
Dieter Nützel
Dieter at nuetzel-hh.de
Fri Jun 29 02:39:26 UTC 2018
For the series:
Tested-by: Dieter Nützel <Dieter at nuetzel-hh.de>
on RX 580
with Plasma 5, UH, UV, Blender 2.79b, Krita 4.1 and glmark2.
Dieter
Am 27.06.2018 22:10, schrieb Marek Olšák:
> From: Marek Olšák <marek.olsak at amd.com>
>
> for vertex color clamping.
> ---
> src/gallium/drivers/radeonsi/si_shader.c | 14 +++++++-------
> src/gallium/drivers/radeonsi/si_shader.h | 9 ++++++---
> 2 files changed, 13 insertions(+), 10 deletions(-)
>
> diff --git a/src/gallium/drivers/radeonsi/si_shader.c
> b/src/gallium/drivers/radeonsi/si_shader.c
> index c6b91ba5cf3..9bee8440027 100644
> --- a/src/gallium/drivers/radeonsi/si_shader.c
> +++ b/src/gallium/drivers/radeonsi/si_shader.c
> @@ -3442,21 +3442,21 @@ static void
> si_set_ls_return_value_for_tcs(struct si_shader_context *ctx)
> ret = si_insert_input_ptr(ctx, ret, ctx->param_rw_buffers,
> 8 + SI_SGPR_RW_BUFFERS);
> ret = si_insert_input_ptr(ctx, ret,
> ctx->param_bindless_samplers_and_images,
> 8 + SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES);
>
> ret = si_insert_input_ret(ctx, ret, ctx->param_vs_state_bits,
> 8 + SI_SGPR_VS_STATE_BITS);
>
> #if !HAVE_32BIT_POINTERS
> - ret = si_insert_input_ptr(ctx, ret, ctx->param_vs_state_bits + 1,
> + ret = si_insert_input_ptr(ctx, ret, ctx->param_vs_state_bits + 4,
> 8 + GFX9_SGPR_2ND_SAMPLERS_AND_IMAGES);
> #endif
>
> ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_layout,
> 8 + GFX9_SGPR_TCS_OFFCHIP_LAYOUT);
> ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_offsets,
> 8 + GFX9_SGPR_TCS_OUT_OFFSETS);
> ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_layout,
> 8 + GFX9_SGPR_TCS_OUT_LAYOUT);
>
> @@ -3482,21 +3482,21 @@ static void
> si_set_es_return_value_for_gs(struct si_shader_context *ctx)
> ret = si_insert_input_ret(ctx, ret, ctx->param_merged_wave_info, 3);
> ret = si_insert_input_ret(ctx, ret, ctx->param_merged_scratch_offset,
> 5);
>
> ret = si_insert_input_ptr(ctx, ret, ctx->param_rw_buffers,
> 8 + SI_SGPR_RW_BUFFERS);
> ret = si_insert_input_ptr(ctx, ret,
> ctx->param_bindless_samplers_and_images,
> 8 + SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES);
>
> #if !HAVE_32BIT_POINTERS
> - ret = si_insert_input_ptr(ctx, ret, ctx->param_vs_state_bits + 1,
> + ret = si_insert_input_ptr(ctx, ret, ctx->param_vs_state_bits + 4,
> 8 + GFX9_SGPR_2ND_SAMPLERS_AND_IMAGES);
> #endif
>
> unsigned vgpr;
> if (ctx->type == PIPE_SHADER_VERTEX)
> vgpr = 8 + GFX9_VSGS_NUM_USER_SGPR;
> else
> vgpr = 8 + GFX9_TESGS_NUM_USER_SGPR;
>
> for (unsigned i = 0; i < 5; i++) {
> @@ -4628,24 +4628,24 @@ static void
> declare_global_desc_pointers(struct si_shader_context *ctx,
> {
> ctx->param_rw_buffers = add_arg(fninfo, ARG_SGPR,
> ac_array_in_const32_addr_space(ctx->v4i32));
> ctx->param_bindless_samplers_and_images = add_arg(fninfo, ARG_SGPR,
> ac_array_in_const32_addr_space(ctx->v8i32));
> }
>
> static void declare_vs_specific_input_sgprs(struct si_shader_context
> *ctx,
> struct si_function_info *fninfo)
> {
> + ctx->param_vs_state_bits = add_arg(fninfo, ARG_SGPR, ctx->i32);
> add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.base_vertex);
> add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.start_instance);
> add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.draw_id);
> - ctx->param_vs_state_bits = add_arg(fninfo, ARG_SGPR, ctx->i32);
> }
>
> static void declare_vs_input_vgprs(struct si_shader_context *ctx,
> struct si_function_info *fninfo,
> unsigned *num_prolog_vgprs)
> {
> struct si_shader *shader = ctx->shader;
>
> add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.vertex_id);
> if (shader->key.as_ls) {
> @@ -4859,27 +4859,26 @@ static void create_function(struct
> si_shader_context *ctx)
> add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused
> (SPI_SHADER_PGM_LO/HI_GS << 8) */
> add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused
> (SPI_SHADER_PGM_LO/HI_GS >> 24) */
>
> declare_global_desc_pointers(ctx, &fninfo);
> declare_per_stage_desc_pointers(ctx, &fninfo,
> (ctx->type == PIPE_SHADER_VERTEX ||
> ctx->type == PIPE_SHADER_TESS_EVAL));
> if (ctx->type == PIPE_SHADER_VERTEX) {
> declare_vs_specific_input_sgprs(ctx, &fninfo);
> } else {
> + ctx->param_vs_state_bits = add_arg(&fninfo, ARG_SGPR, ctx->i32);
> ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR,
> ctx->i32);
> ctx->param_tes_offchip_addr = add_arg(&fninfo, ARG_SGPR, ctx->i32);
> - if (!HAVE_32BIT_POINTERS) {
> - /* Declare as many input SGPRs as the VS has. */
> + /* Declare as many input SGPRs as the VS has. */
> + if (!HAVE_32BIT_POINTERS)
> add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
> - ctx->param_vs_state_bits = add_arg(&fninfo, ARG_SGPR, ctx->i32);
> /* unused */
> - }
> }
>
> if (!HAVE_32BIT_POINTERS) {
> declare_samplers_and_images(ctx, &fninfo,
> ctx->type == PIPE_SHADER_GEOMETRY);
> }
> if (ctx->type == PIPE_SHADER_VERTEX) {
> ctx->param_vertex_buffers = add_arg(&fninfo, ARG_SGPR,
> ac_array_in_const32_addr_space(ctx->v4i32));
> }
> @@ -4911,20 +4910,21 @@ static void create_function(struct
> si_shader_context *ctx)
> for (i = 0; i < 8 + num_user_sgprs; i++)
> returns[num_returns++] = ctx->i32; /* SGPRs */
> for (i = 0; i < 5; i++)
> returns[num_returns++] = ctx->f32; /* VGPRs */
> }
> break;
>
> case PIPE_SHADER_TESS_EVAL:
> declare_global_desc_pointers(ctx, &fninfo);
> declare_per_stage_desc_pointers(ctx, &fninfo, true);
> + ctx->param_vs_state_bits = add_arg(&fninfo, ARG_SGPR, ctx->i32);
> ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR,
> ctx->i32);
> ctx->param_tes_offchip_addr = add_arg(&fninfo, ARG_SGPR, ctx->i32);
>
> if (shader->key.as_es) {
> ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR,
> ctx->i32);
> add_arg(&fninfo, ARG_SGPR, ctx->i32);
> ctx->param_es2gs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
> } else {
> add_arg(&fninfo, ARG_SGPR, ctx->i32);
> declare_streamout_params(ctx, &shader->selector->so,
> diff --git a/src/gallium/drivers/radeonsi/si_shader.h
> b/src/gallium/drivers/radeonsi/si_shader.h
> index fd2f71bed74..bba4d4f9018 100644
> --- a/src/gallium/drivers/radeonsi/si_shader.h
> +++ b/src/gallium/drivers/radeonsi/si_shader.h
> @@ -167,31 +167,34 @@ enum {
> SI_SGPR_CONST_AND_SHADER_BUFFERS, /* or just a constant buffer 0
> pointer */
> #if !HAVE_32BIT_POINTERS
> SI_SGPR_CONST_AND_SHADER_BUFFERS_HI,
> #endif
> SI_SGPR_SAMPLERS_AND_IMAGES,
> #if !HAVE_32BIT_POINTERS
> SI_SGPR_SAMPLERS_AND_IMAGES_HI,
> #endif
> SI_NUM_RESOURCE_SGPRS,
>
> + /* API VS, TES without GS, GS copy shader */
> + SI_SGPR_VS_STATE_BITS = SI_NUM_RESOURCE_SGPRS,
> + SI_NUM_VS_STATE_RESOURCE_SGPRS,
> +
> /* all VS variants */
> - SI_SGPR_BASE_VERTEX = SI_NUM_RESOURCE_SGPRS,
> + SI_SGPR_BASE_VERTEX = SI_NUM_VS_STATE_RESOURCE_SGPRS,
> SI_SGPR_START_INSTANCE,
> SI_SGPR_DRAWID,
> - SI_SGPR_VS_STATE_BITS,
> SI_VS_NUM_USER_SGPR,
>
> SI_SGPR_VS_BLIT_DATA = SI_SGPR_CONST_AND_SHADER_BUFFERS,
>
> /* TES */
> - SI_SGPR_TES_OFFCHIP_LAYOUT = SI_NUM_RESOURCE_SGPRS,
> + SI_SGPR_TES_OFFCHIP_LAYOUT = SI_NUM_VS_STATE_RESOURCE_SGPRS,
> SI_SGPR_TES_OFFCHIP_ADDR,
> SI_TES_NUM_USER_SGPR,
>
> /* GFX6-8: TCS only */
> GFX6_SGPR_TCS_OFFCHIP_LAYOUT = SI_NUM_RESOURCE_SGPRS,
> GFX6_SGPR_TCS_OUT_OFFSETS,
> GFX6_SGPR_TCS_OUT_LAYOUT,
> GFX6_SGPR_TCS_IN_LAYOUT,
> GFX6_TCS_NUM_USER_SGPR,
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