[Mesa-dev] [PATCH 20/22] i965/vec4: Relax writemask condition in CSE

[Ian Romanick]

On 03/05/2018 02:50 PM, Kenneth Graunke wrote:
> On Friday, February 23, 2018 3:56:05 PM PST Ian Romanick wrote:
>> From: Ian Romanick <ian.d.romanick at intel.com>
>>
>> If the previously seen instruction generates more fields than the new
>> instruction, still allow CSE to happen.  This doesn't do much, but it
>> also enables a couple more shaders in the next patch.  It helped quite a
>> bit in another change series that I have (at least for now) abandoned.
>>
>> No changes on Skylake, Broadwell, Iron Lake or GM45.
> 
> Skylake and Broadwell sort of go without saying, they don't use this
> compiler :)
> 
> It might be worth leaving some kind of comment (or renaming variables?)
> in instructions_match() to indicate that 'a' is the generating
> expression and 'b' is the second instance...since it's no longer
> exactly symmetrical.

I thought about that... I just couldn't come up with any names that I
actually liked.  Do you have any favorites? :)

> Either way,
> Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

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