[Mesa-dev] [PATCH 18/22 v4] squash! i965/fs: Add infrastructure for generating CSEL instructions.

[Ian Romanick]

From: Ian Romanick <ian.d.romanick at intel.com>

v4: Only set BRW_ALIGN_16 on Gen < 10 (suggested by Matt).  Don't reset
the access mode afterwards (suggested by Samuel and Matt).  Add support
for CSEL not modifying the flags to more places (requested by Matt).

Reviewed-by: Matt Turner <mattst88 at gmail.com>
---
 src/intel/compiler/brw_disasm.c         | 1 +
 src/intel/compiler/brw_fs.cpp           | 1 +
 src/intel/compiler/brw_fs_generator.cpp | 5 +++--
 src/intel/compiler/brw_ir_vec4.h        | 1 +
 src/intel/compiler/brw_vec4.cpp         | 1 +
 5 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/src/intel/compiler/brw_disasm.c b/src/intel/compiler/brw_disasm.c
index a9a108f..5f75c67 100644
--- a/src/intel/compiler/brw_disasm.c
+++ b/src/intel/compiler/brw_disasm.c
@@ -1508,6 +1508,7 @@ brw_disassemble_inst(FILE *file, const struct gen_device_info *devinfo,
        */
       if (brw_inst_cond_modifier(devinfo, inst) &&
           (devinfo->gen < 6 || (opcode != BRW_OPCODE_SEL &&
+                                opcode != BRW_OPCODE_CSEL &&
                                 opcode != BRW_OPCODE_IF &&
                                 opcode != BRW_OPCODE_WHILE))) {
          format(file, ".f%"PRIu64,
diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index f532c2c..f4cc941 100644
--- a/src/intel/compiler/brw_fs.cpp
+++ b/src/intel/compiler/brw_fs.cpp
@@ -5544,6 +5544,7 @@ fs_visitor::dump_instruction(backend_instruction *be_inst, FILE *file)
       fprintf(file, "%s", conditional_modifier[inst->conditional_mod]);
       if (!inst->predicate &&
           (devinfo->gen < 5 || (inst->opcode != BRW_OPCODE_SEL &&
+                                inst->opcode != BRW_OPCODE_CSEL &&
                                 inst->opcode != BRW_OPCODE_IF &&
                                 inst->opcode != BRW_OPCODE_WHILE))) {
          fprintf(file, ".f%d.%d", inst->flag_subreg / 2,
diff --git a/src/intel/compiler/brw_fs_generator.cpp b/src/intel/compiler/brw_fs_generator.cpp
index 97d2357..85a6183 100644
--- a/src/intel/compiler/brw_fs_generator.cpp
+++ b/src/intel/compiler/brw_fs_generator.cpp
@@ -1876,9 +1876,10 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width)
 	 brw_SEL(p, dst, src[0], src[1]);
 	 break;
       case BRW_OPCODE_CSEL:
-         brw_set_default_access_mode(p, BRW_ALIGN_16);
+         assert(devinfo->gen >= 8);
+         if (devinfo->gen < 10)
+            brw_set_default_access_mode(p, BRW_ALIGN_16);
          brw_CSEL(p, dst, src[0], src[1], src[2]);
-         brw_set_default_access_mode(p, BRW_ALIGN_1);
          break;
       case BRW_OPCODE_BFREV:
          assert(devinfo->gen >= 7);
diff --git a/src/intel/compiler/brw_ir_vec4.h b/src/intel/compiler/brw_ir_vec4.h
index a0e6402..cbaff2f 100644
--- a/src/intel/compiler/brw_ir_vec4.h
+++ b/src/intel/compiler/brw_ir_vec4.h
@@ -329,6 +329,7 @@ public:
    bool writes_flag()
    {
       return (conditional_mod && (opcode != BRW_OPCODE_SEL &&
+                                  opcode != BRW_OPCODE_CSEL &&
                                   opcode != BRW_OPCODE_IF &&
                                   opcode != BRW_OPCODE_WHILE));
    }
diff --git a/src/intel/compiler/brw_vec4.cpp b/src/intel/compiler/brw_vec4.cpp
index ac6b997..e483814 100644
--- a/src/intel/compiler/brw_vec4.cpp
+++ b/src/intel/compiler/brw_vec4.cpp
@@ -1557,6 +1557,7 @@ vec4_visitor::dump_instruction(backend_instruction *be_inst, FILE *file)
       fprintf(file, "%s", conditional_modifier[inst->conditional_mod]);
       if (!inst->predicate &&
           (devinfo->gen < 5 || (inst->opcode != BRW_OPCODE_SEL &&
+                                inst->opcode != BRW_OPCODE_CSEL &&
                                 inst->opcode != BRW_OPCODE_IF &&
                                 inst->opcode != BRW_OPCODE_WHILE))) {
          fprintf(file, ".f%d.%d", inst->flag_subreg / 2, inst->flag_subreg % 2);
-- 
2.9.5