[Mesa-dev] [RFC PATCH 3/9] ac/shader: count the number of input PS interp

[Samuel Pitoiset]

This adds a new level of gathering ("post-analysis") because
we have to bump the number of interp when the layer is needed.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
---
 src/amd/common/ac_nir_to_llvm.c |  1 -
 src/amd/common/ac_nir_to_llvm.h |  1 -
 src/amd/common/ac_shader_info.c | 35 +++++++++++++++++++++++++++++++++++
 src/amd/common/ac_shader_info.h |  1 +
 src/amd/vulkan/radv_pipeline.c  |  2 +-
 src/amd/vulkan/radv_shader.c    |  2 +-
 6 files changed, 38 insertions(+), 4 deletions(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 358e3f04fd..ff954be97c 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -5611,7 +5611,6 @@ handle_fs_inputs(struct radv_shader_context *ctx,
 						  ctx->abi.frag_pos[3]);
 		}
 	}
-	ctx->shader_info->fs.num_interp = index;
 	ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
 
 	if (ctx->shader_info->info.needs_multiview_view_index)
diff --git a/src/amd/common/ac_nir_to_llvm.h b/src/amd/common/ac_nir_to_llvm.h
index 983189eb93..42a58e7d79 100644
--- a/src/amd/common/ac_nir_to_llvm.h
+++ b/src/amd/common/ac_nir_to_llvm.h
@@ -175,7 +175,6 @@ struct ac_shader_variant_info {
 			uint64_t outputs_written;
 		} vs;
 		struct {
-			unsigned num_interp;
 			uint32_t input_mask;
 			uint32_t flat_shaded_mask;
 			bool can_discard;
diff --git a/src/amd/common/ac_shader_info.c b/src/amd/common/ac_shader_info.c
index 60e3d62e79..2a99cecdd7 100644
--- a/src/amd/common/ac_shader_info.c
+++ b/src/amd/common/ac_shader_info.c
@@ -213,6 +213,7 @@ static void
 gather_info_input_decl_ps(const nir_shader *nir, const nir_variable *var,
 			  struct ac_shader_info *info)
 {
+	unsigned attrib_count = glsl_count_attribute_slots(var->type, false);
 	const struct glsl_type *type = glsl_without_array(var->type);
 	int idx = var->data.location;
 
@@ -251,6 +252,13 @@ gather_info_input_decl_ps(const nir_shader *nir, const nir_variable *var,
 	} else {
 		info->ps.input_interp_mode[idx] = INTERP_MODE_FLAT;
 	}
+
+	if (idx >= VARYING_SLOT_VAR0 ||
+	    idx == VARYING_SLOT_PNTC ||
+	    idx == VARYING_SLOT_PRIMITIVE_ID ||
+	    idx == VARYING_SLOT_LAYER) {
+		info->ps.num_interp += attrib_count;
+	}
 }
 
 static void
@@ -303,6 +311,31 @@ gather_info_output_decl(const nir_shader *nir, const nir_variable *var,
 	}
 }
 
+static void
+gather_info_shader_ps(const nir_shader *nir, struct ac_shader_info *info)
+{
+	if (!info->ps.layer_input &&
+	    (info->ps.uses_input_attachments ||
+	     info->needs_multiview_view_index)) {
+		/* VARYING_SLOT_LAYER is needed for subpass attachments, but do
+		 * not count it twice if it's already declared in the shader.
+		 */
+		info->ps.num_interp++;
+	}
+}
+
+static void
+gather_info_shader(const nir_shader *nir, struct ac_shader_info *info)
+{
+	switch (nir->info.stage) {
+	case MESA_SHADER_FRAGMENT:
+		gather_info_shader_ps(nir, info);
+		break;
+	default:
+		break;
+	}
+}
+
 void
 ac_nir_shader_info_pass(const struct nir_shader *nir,
 			const struct ac_nir_compiler_options *options,
@@ -323,4 +356,6 @@ ac_nir_shader_info_pass(const struct nir_shader *nir,
 
 	nir_foreach_variable(variable, &nir->outputs)
 		gather_info_output_decl(nir, variable, info);
+
+	gather_info_shader(nir, info);
 }
diff --git a/src/amd/common/ac_shader_info.h b/src/amd/common/ac_shader_info.h
index d02841adfe..12493aead7 100644
--- a/src/amd/common/ac_shader_info.h
+++ b/src/amd/common/ac_shader_info.h
@@ -46,6 +46,7 @@ struct ac_shader_info {
 		uint8_t output_usage_mask[VARYING_SLOT_VAR31 + 1];
 	} tes;
 	struct {
+		unsigned num_interp;
 		bool force_persample;
 		bool needs_sample_positions;
 		bool uses_input_attachments;
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index f8f09a7e16..87de1021c0 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -2851,7 +2851,7 @@ radv_pipeline_generate_fragment_shader(struct radeon_winsys_cs *cs,
 			       ps->config.spi_ps_input_addr);
 
 	radeon_set_context_reg(cs, R_0286D8_SPI_PS_IN_CONTROL,
-			       S_0286D8_NUM_INTERP(ps->info.fs.num_interp));
+			       S_0286D8_NUM_INTERP(ps->info.info.ps.num_interp));
 
 	radeon_set_context_reg(cs, R_0286E0_SPI_BARYC_CNTL, pipeline->graphics.spi_baryc_cntl);
 
diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index 85672e600d..4ff209c1ab 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -614,7 +614,7 @@ generate_shader_stats(struct radv_device *device,
 
 	if (stage == MESA_SHADER_FRAGMENT) {
 		lds_per_wave = conf->lds_size * lds_increment +
-			       align(variant->info.fs.num_interp * 48,
+			       align(variant->info.info.ps.num_interp * 48,
 				     lds_increment);
 	}
 
-- 
2.16.2