[Mesa-dev] [PATCH v4 18/18] intel: Remove use_clear_address flag from isl_surf_fill_state_info.
Rafael Antognolli
rafael.antognolli at intel.com
Thu Mar 8 16:49:11 UTC 2018
This flag was used while porting parts of the code to use the clear
color address, but other parts were not ported yet. So isl had to be
flexible enough to support both cases.
Now that the code is using exclusively clear color address for
everything Gen10+, we don't need it anymore.
Signed-off-by: Rafael Antognolli <rafael.antognolli at intel.com>
---
src/intel/blorp/blorp_genX_exec.h | 4 ----
src/intel/isl/isl.c | 2 +-
src/intel/isl/isl.h | 7 +++----
src/intel/isl/isl_surface_state.c | 21 +++++++--------------
src/intel/vulkan/anv_image.c | 1 -
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 7 ++-----
6 files changed, 13 insertions(+), 29 deletions(-)
diff --git a/src/intel/blorp/blorp_genX_exec.h b/src/intel/blorp/blorp_genX_exec.h
index eef6ed8291a..29e426fbb9c 100644
--- a/src/intel/blorp/blorp_genX_exec.h
+++ b/src/intel/blorp/blorp_genX_exec.h
@@ -1314,15 +1314,11 @@ blorp_emit_surface_state(struct blorp_batch *batch,
write_disable_mask |= ISL_CHANNEL_ALPHA_BIT;
}
- const bool use_clear_address =
- GEN_GEN >= 10 && (surface->clear_color_addr.buffer != NULL);
-
isl_surf_fill_state(batch->blorp->isl_dev, state,
.surf = &surf, .view = &surface->view,
.aux_surf = &surface->aux_surf, .aux_usage = aux_usage,
.mocs = surface->addr.mocs,
.clear_color = surface->clear_color,
- .use_clear_address = use_clear_address,
.write_disables = write_disable_mask);
blorp_surface_reloc(batch, state_offset + isl_dev->ss.addr_offset,
diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index 3566bd3f0dd..d0cd7313bc6 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -79,7 +79,7 @@ isl_device_init(struct isl_device *dev,
RENDER_SURFACE_STATE_ClearValueAddress_start(info) / 32 * 4;
}
- if (ISL_DEV_GEN(dev) <= 10) {
+ if (ISL_DEV_GEN(dev) < 10) {
dev->ss.clear_value_size =
isl_align(RENDER_SURFACE_STATE_RedClearColor_bits(info) +
RENDER_SURFACE_STATE_GreenClearColor_bits(info) +
diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h
index c50b78d4701..d65c621a732 100644
--- a/src/intel/isl/isl.h
+++ b/src/intel/isl/isl.h
@@ -1308,12 +1308,11 @@ struct isl_surf_fill_state_info {
union isl_color_value clear_color;
/**
- * Send only the clear value address
+ * The address of the clear color state buffer
*
- * If set, we only pass the clear address to the GPU and it will fetch it
- * from wherever it is.
+ * On gen10+, we use an address to the indirect clear color, stored in a
+ * state buffer.
*/
- bool use_clear_address;
uint64_t clear_address;
/**
diff --git a/src/intel/isl/isl_surface_state.c b/src/intel/isl/isl_surface_state.c
index bff9693f02d..77931f25aa3 100644
--- a/src/intel/isl/isl_surface_state.c
+++ b/src/intel/isl/isl_surface_state.c
@@ -637,21 +637,14 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state,
#endif
if (info->aux_usage != ISL_AUX_USAGE_NONE) {
- if (info->use_clear_address) {
#if GEN_GEN >= 10
- s.ClearValueAddressEnable = true;
- s.ClearValueAddress = info->clear_address;
-#else
- unreachable("Gen9 and earlier do not support indirect clear colors");
-#endif
- }
-#if GEN_GEN >= 9
- if (!info->use_clear_address) {
- s.RedClearColor = info->clear_color.u32[0];
- s.GreenClearColor = info->clear_color.u32[1];
- s.BlueClearColor = info->clear_color.u32[2];
- s.AlphaClearColor = info->clear_color.u32[3];
- }
+ s.ClearValueAddressEnable = true;
+ s.ClearValueAddress = info->clear_address;
+#elif GEN_GEN >= 9
+ s.RedClearColor = info->clear_color.u32[0];
+ s.GreenClearColor = info->clear_color.u32[1];
+ s.BlueClearColor = info->clear_color.u32[2];
+ s.AlphaClearColor = info->clear_color.u32[3];
#elif GEN_GEN >= 7
/* Prior to Sky Lake, we only have one bit for the clear color which
* gives us 0 or 1 in whatever the surface's format happens to be.
diff --git a/src/intel/vulkan/anv_image.c b/src/intel/vulkan/anv_image.c
index a941559eb3a..7f16b3dd5f2 100644
--- a/src/intel/vulkan/anv_image.c
+++ b/src/intel/vulkan/anv_image.c
@@ -1162,7 +1162,6 @@ anv_image_fill_surface_state(struct anv_device *device,
.aux_usage = aux_usage,
.aux_address = aux_address,
.clear_address = clear_address.offset,
- .use_clear_address = clear_address.bo != NULL,
.mocs = device->default_mocs,
.x_offset_sa = tile_x_sa,
.y_offset_sa = tile_y_sa);
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 268effef397..7d1ddbc5ed0 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -186,11 +186,9 @@ brw_emit_surface_state(struct brw_context *brw,
brw->isl_dev.ss.align,
surf_offset);
- bool use_clear_address = devinfo->gen >= 10 && aux_surf;
-
struct brw_bo *clear_bo = NULL;
uint32_t clear_offset = 0;
- if (use_clear_address) {
+ if (devinfo->gen >= 10 && aux_surf) {
if (mt->mcs_buf && mt->mcs_buf->clear_color_bo) {
clear_bo = mt->mcs_buf->clear_color_bo;
clear_offset = mt->mcs_buf->clear_color_offset;
@@ -208,7 +206,6 @@ brw_emit_surface_state(struct brw_context *brw,
.aux_address = aux_offset,
.mocs = brw_get_bo_mocs(devinfo, mt->bo),
.clear_color = clear_color,
- .use_clear_address = use_clear_address,
.clear_address = clear_offset,
.x_offset_sa = tile_x, .y_offset_sa = tile_y);
if (aux_surf) {
@@ -240,7 +237,7 @@ brw_emit_surface_state(struct brw_context *brw,
}
}
- if (use_clear_address) {
+ if (devinfo->gen >= 10 && aux_surf) {
/* Make sure the offset is aligned with a cacheline. */
assert((clear_offset & 0x3f) == 0);
uint32_t *clear_address =
--
2.14.3
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