[Mesa-dev] [PATCH 14/50] glsl: Add "built-in" functions to do fp32_to_fp64(fp32)

Dave Airlie airlied at gmail.com
Tue Mar 13 04:24:39 UTC 2018


From: Elie Tournier <tournier.elie at gmail.com>

Signed-off-by: Elie Tournier <elie.tournier at collabora.com>
---
 src/compiler/glsl/builtin_float64.h     | 192 ++++++++++++++++++++++++++++++++
 src/compiler/glsl/builtin_functions.cpp |   4 +
 src/compiler/glsl/builtin_functions.h   |   3 +
 src/compiler/glsl/float64.glsl          |  38 +++++++
 src/compiler/glsl/glcpp/glcpp-parse.y   |   1 +
 5 files changed, 238 insertions(+)

diff --git a/src/compiler/glsl/builtin_float64.h b/src/compiler/glsl/builtin_float64.h
index f937a2f..034d2d0 100644
--- a/src/compiler/glsl/builtin_float64.h
+++ b/src/compiler/glsl/builtin_float64.h
@@ -6050,3 +6050,195 @@ fp64_to_fp32(void *mem_ctx, builtin_available_predicate avail)
    sig->replace_parameters(&sig_parameters);
    return sig;
 }
+ir_function_signature *
+fp32_to_fp64(void *mem_ctx, builtin_available_predicate avail)
+{
+   ir_function_signature *const sig =
+      new(mem_ctx) ir_function_signature(glsl_type::uvec2_type, avail);
+   ir_factory body(&sig->body, mem_ctx);
+   sig->is_defined = true;
+
+   exec_list sig_parameters;
+
+   ir_variable *const r097F = new(mem_ctx) ir_variable(glsl_type::float_type, "f", ir_var_function_in);
+   sig_parameters.push_tail(r097F);
+   ir_variable *const r0980 = body.make_temp(glsl_type::bool_type, "execute_flag");
+   body.emit(assign(r0980, body.constant(true), 0x01));
+
+   ir_variable *const r0981 = body.make_temp(glsl_type::uvec2_type, "return_value");
+   ir_variable *const r0982 = new(mem_ctx) ir_variable(glsl_type::uint_type, "aSign", ir_var_auto);
+   body.emit(r0982);
+   ir_variable *const r0983 = new(mem_ctx) ir_variable(glsl_type::int_type, "aExp", ir_var_auto);
+   body.emit(r0983);
+   ir_variable *const r0984 = new(mem_ctx) ir_variable(glsl_type::uint_type, "aFrac", ir_var_auto);
+   body.emit(r0984);
+   ir_variable *const r0985 = body.make_temp(glsl_type::uint_type, "floatBitsToUint_retval");
+   body.emit(assign(r0985, expr(ir_unop_bitcast_f2u, r097F), 0x01));
+
+   ir_variable *const r0986 = body.make_temp(glsl_type::uint_type, "assignment_tmp");
+   body.emit(assign(r0986, bit_and(r0985, body.constant(8388607u)), 0x01));
+
+   body.emit(assign(r0984, r0986, 0x01));
+
+   ir_variable *const r0987 = body.make_temp(glsl_type::int_type, "assignment_tmp");
+   ir_expression *const r0988 = rshift(r0985, body.constant(int(23)));
+   ir_expression *const r0989 = bit_and(r0988, body.constant(255u));
+   body.emit(assign(r0987, expr(ir_unop_u2i, r0989), 0x01));
+
+   body.emit(assign(r0983, r0987, 0x01));
+
+   body.emit(assign(r0982, rshift(r0985, body.constant(int(31))), 0x01));
+
+   /* IF CONDITION */
+   ir_expression *const r098B = equal(r0987, body.constant(int(255)));
+   ir_if *f098A = new(mem_ctx) ir_if(operand(r098B).val);
+   exec_list *const f098A_parent_instructions = body.instructions;
+
+      /* THEN INSTRUCTIONS */
+      body.instructions = &f098A->then_instructions;
+
+      /* IF CONDITION */
+      ir_expression *const r098D = nequal(r0986, body.constant(0u));
+      ir_if *f098C = new(mem_ctx) ir_if(operand(r098D).val);
+      exec_list *const f098C_parent_instructions = body.instructions;
+
+         /* THEN INSTRUCTIONS */
+         body.instructions = &f098C->then_instructions;
+
+         ir_variable *const r098E = body.make_temp(glsl_type::uint_type, "assignment_tmp");
+         body.emit(assign(r098E, lshift(r0985, body.constant(int(9))), 0x01));
+
+         ir_variable *const r098F = body.make_temp(glsl_type::uvec2_type, "vec_ctor");
+         ir_expression *const r0990 = lshift(r098E, body.constant(int(20)));
+         body.emit(assign(r098F, bit_or(r0990, body.constant(0u)), 0x01));
+
+         ir_expression *const r0991 = rshift(r098E, body.constant(int(12)));
+         ir_expression *const r0992 = lshift(r0982, body.constant(int(31)));
+         ir_expression *const r0993 = bit_or(r0992, body.constant(2146959360u));
+         body.emit(assign(r098F, bit_or(r0991, r0993), 0x02));
+
+         body.emit(assign(r0981, r098F, 0x03));
+
+         body.emit(assign(r0980, body.constant(false), 0x01));
+
+
+         /* ELSE INSTRUCTIONS */
+         body.instructions = &f098C->else_instructions;
+
+         ir_variable *const r0994 = new(mem_ctx) ir_variable(glsl_type::uvec2_type, "z", ir_var_auto);
+         body.emit(r0994);
+         ir_expression *const r0995 = lshift(r0982, body.constant(int(31)));
+         body.emit(assign(r0994, add(r0995, body.constant(2146435072u)), 0x02));
+
+         body.emit(assign(r0994, body.constant(0u), 0x01));
+
+         body.emit(assign(r0981, r0994, 0x03));
+
+         body.emit(assign(r0980, body.constant(false), 0x01));
+
+
+      body.instructions = f098C_parent_instructions;
+      body.emit(f098C);
+
+      /* END IF */
+
+
+      /* ELSE INSTRUCTIONS */
+      body.instructions = &f098A->else_instructions;
+
+      /* IF CONDITION */
+      ir_expression *const r0997 = equal(r0987, body.constant(int(0)));
+      ir_if *f0996 = new(mem_ctx) ir_if(operand(r0997).val);
+      exec_list *const f0996_parent_instructions = body.instructions;
+
+         /* THEN INSTRUCTIONS */
+         body.instructions = &f0996->then_instructions;
+
+         /* IF CONDITION */
+         ir_expression *const r0999 = equal(r0986, body.constant(0u));
+         ir_if *f0998 = new(mem_ctx) ir_if(operand(r0999).val);
+         exec_list *const f0998_parent_instructions = body.instructions;
+
+            /* THEN INSTRUCTIONS */
+            body.instructions = &f0998->then_instructions;
+
+            ir_variable *const r099A = new(mem_ctx) ir_variable(glsl_type::uvec2_type, "z", ir_var_auto);
+            body.emit(r099A);
+            body.emit(assign(r099A, lshift(r0982, body.constant(int(31))), 0x02));
+
+            body.emit(assign(r099A, body.constant(0u), 0x01));
+
+            body.emit(assign(r0981, r099A, 0x03));
+
+            body.emit(assign(r0980, body.constant(false), 0x01));
+
+
+            /* ELSE INSTRUCTIONS */
+            body.instructions = &f0998->else_instructions;
+
+            ir_variable *const r099B = body.make_temp(glsl_type::int_type, "assignment_tmp");
+            ir_expression *const r099C = equal(r0986, body.constant(0u));
+            ir_expression *const r099D = expr(ir_unop_find_msb, r0986);
+            ir_expression *const r099E = sub(body.constant(int(31)), r099D);
+            ir_expression *const r099F = expr(ir_triop_csel, r099C, body.constant(int(32)), r099E);
+            body.emit(assign(r099B, add(r099F, body.constant(int(-8))), 0x01));
+
+            body.emit(assign(r0984, lshift(r0986, r099B), 0x01));
+
+            body.emit(assign(r0983, sub(body.constant(int(1)), r099B), 0x01));
+
+            body.emit(assign(r0983, add(r0983, body.constant(int(-1))), 0x01));
+
+
+         body.instructions = f0998_parent_instructions;
+         body.emit(f0998);
+
+         /* END IF */
+
+
+      body.instructions = f0996_parent_instructions;
+      body.emit(f0996);
+
+      /* END IF */
+
+      /* IF CONDITION */
+      ir_if *f09A0 = new(mem_ctx) ir_if(operand(r0980).val);
+      exec_list *const f09A0_parent_instructions = body.instructions;
+
+         /* THEN INSTRUCTIONS */
+         body.instructions = &f09A0->then_instructions;
+
+         ir_variable *const r09A1 = new(mem_ctx) ir_variable(glsl_type::uvec2_type, "z", ir_var_auto);
+         body.emit(r09A1);
+         ir_expression *const r09A2 = lshift(r0982, body.constant(int(31)));
+         ir_expression *const r09A3 = add(r0983, body.constant(int(896)));
+         ir_expression *const r09A4 = expr(ir_unop_i2u, r09A3);
+         ir_expression *const r09A5 = lshift(r09A4, body.constant(int(20)));
+         ir_expression *const r09A6 = add(r09A2, r09A5);
+         ir_expression *const r09A7 = rshift(r0984, body.constant(int(3)));
+         body.emit(assign(r09A1, add(r09A6, r09A7), 0x02));
+
+         ir_expression *const r09A8 = lshift(r0984, body.constant(int(29)));
+         body.emit(assign(r09A1, bit_or(r09A8, body.constant(0u)), 0x01));
+
+         body.emit(assign(r0981, r09A1, 0x03));
+
+         body.emit(assign(r0980, body.constant(false), 0x01));
+
+
+      body.instructions = f09A0_parent_instructions;
+      body.emit(f09A0);
+
+      /* END IF */
+
+
+   body.instructions = f098A_parent_instructions;
+   body.emit(f098A);
+
+   /* END IF */
+
+   body.emit(ret(r0981));
+
+   sig->replace_parameters(&sig_parameters);
+   return sig;
+}
diff --git a/src/compiler/glsl/builtin_functions.cpp b/src/compiler/glsl/builtin_functions.cpp
index b0aa2e3..48e0b20 100644
--- a/src/compiler/glsl/builtin_functions.cpp
+++ b/src/compiler/glsl/builtin_functions.cpp
@@ -3390,6 +3390,10 @@ builtin_builder::create_builtins()
                 generate_ir::fp64_to_fp32(mem_ctx, integer_functions_supported),
                 NULL);
 
+   add_function("__builtin_fp32_to_fp64",
+                generate_ir::int_to_fp64(mem_ctx, integer_functions_supported),
+                NULL);
+
 #undef F
 #undef FI
 #undef FIUD_VEC
diff --git a/src/compiler/glsl/builtin_functions.h b/src/compiler/glsl/builtin_functions.h
index a6e2192..f9cc0ad 100644
--- a/src/compiler/glsl/builtin_functions.h
+++ b/src/compiler/glsl/builtin_functions.h
@@ -103,6 +103,9 @@ int_to_fp64(void *mem_ctx, builtin_available_predicate avail);
 ir_function_signature *
 fp64_to_fp32(void *mem_ctx, builtin_available_predicate avail);
 
+ir_function_signature *
+fp32_to_fp64(void *mem_ctx, builtin_available_predicate avail);
+
 }
 
 #endif /* BULITIN_FUNCTIONS_H */
diff --git a/src/compiler/glsl/float64.glsl b/src/compiler/glsl/float64.glsl
index ec6b80c..748e4af 100644
--- a/src/compiler/glsl/float64.glsl
+++ b/src/compiler/glsl/float64.glsl
@@ -976,3 +976,41 @@ fp64_to_fp32(uvec2 a)
    zFrac = mix(zFrac, zFrac | 0x40000000u, aExp != 0);
    return roundAndPackFloat32(aSign, aExp - 0x381, zFrac);
 }
+
+/* Returns the result of converting the single-precision floating-point value
+ * `a' to the double-precision floating-point format.
+ */
+uvec2
+fp32_to_fp64(float f)
+{
+   uint a = floatBitsToUint(f);
+   uint aFrac = a & 0x007FFFFFu;
+   int aExp = int((a>>23) & 0xFFu);
+   uint aSign = a>>31;
+   uint zFrac0 = 0u;
+   uint zFrac1 = 0u;
+
+   if (aExp == 0xFF) {
+      if (aFrac != 0u) {
+         uint nanLo = 0u;
+         uint nanHi = a<<9;
+         shift64Right(nanHi, nanLo, 12, nanHi, nanLo);
+         nanHi |= ((aSign<<31) | 0x7FF80000u);
+         return uvec2(nanLo, nanHi);
+      }
+      return packFloat64(aSign, 0x7FF, 0u, 0u);
+    }
+
+   if (aExp == 0) {
+      if (aFrac == 0u)
+         return packFloat64(aSign, 0, 0u, 0u);
+      /* Normalize subnormal */
+      int shiftCount = countLeadingZeros32(aFrac) - 8;
+      aFrac <<= shiftCount;
+      aExp = 1 - shiftCount;
+      --aExp;
+   }
+
+   shift64Right(aFrac, 0u, 3, zFrac0, zFrac1);
+   return packFloat64(aSign, aExp + 0x380, zFrac0, zFrac1);
+}
diff --git a/src/compiler/glsl/glcpp/glcpp-parse.y b/src/compiler/glsl/glcpp/glcpp-parse.y
index bc85026..3fcdcb0 100644
--- a/src/compiler/glsl/glcpp/glcpp-parse.y
+++ b/src/compiler/glsl/glcpp/glcpp-parse.y
@@ -2380,6 +2380,7 @@ _glcpp_parser_handle_version_declaration(glcpp_parser_t *parser, intmax_t versio
          add_builtin_define(parser, "__have_builtin_builtin_fp64_to_int", 1);
          add_builtin_define(parser, "__have_builtin_builtin_int_to_fp64", 1);
          add_builtin_define(parser, "__have_builtin_builtin_fp64_to_fp32", 1);
+         add_builtin_define(parser, "__have_builtin_builtin_fp32_to_fp64", 1);
       }
    }
 
-- 
2.9.5



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