[Mesa-dev] [PATCH 4/5] i965/miptree: Map with movntdqa for linear buffers only

[Nanley Chery]

On Tue, Jan 09, 2018 at 11:17:01PM -0800, Scott D Phillips wrote:
> Removes a place where gtt mapping is used.
> ---
>  src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 

This patch is
Reviewed-by: Nanley Chery <nanley.g.chery at intel.com>

> diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> index e4a3f163d2..fa4ae06399 100644
> --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> @@ -3707,7 +3707,8 @@ intel_miptree_map(struct brw_context *brw,
>  #if defined(USE_SSE41)
>     } else if (!(mode & GL_MAP_WRITE_BIT) &&
>                !mt->compressed && cpu_has_sse4_1 &&
> -              (mt->surf.row_pitch % 16 == 0)) {
> +              (mt->surf.row_pitch % 16 == 0) &&
> +              (mt->surf.tiling == ISL_TILING_LINEAR)) {
>        intel_miptree_map_movntdqa(brw, mt, map, level, slice);
>  #endif
>     } else if (mt->surf.tiling != ISL_TILING_LINEAR) {
> @@ -3752,6 +3753,7 @@ intel_miptree_unmap(struct brw_context *brw,
>     } else if (!(map->mode & GL_MAP_WRITE_BIT) &&
>                !mt->compressed && cpu_has_sse4_1 &&
>                (mt->surf.row_pitch % 16 == 0) &&
> +              (mt->surf.tiling == ISL_TILING_LINEAR) &&
>                map->buffer) {
>        intel_miptree_unmap_movntdqa(brw, mt, map, level, slice);
>  #endif
> -- 
> 2.14.3
> 
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