[Mesa-dev] [PATCH] radv/query: handle multiview queries properly.
Dave Airlie
airlied at gmail.com
Thu Mar 15 20:25:43 UTC 2018
From: Dave Airlie <airlied at redhat.com>
For multiview we need to emit a number of sequential queries
depending on the view mask.
This avoids dEQP-VK.multiview.queries.15 waiting forever
on the CPU for query results that are never coming.
This doesn't make this test pass though, but I can now
finish my CTS run.
Signed-off-by: Dave Airlie <airlied at redhat.com>
---
src/amd/vulkan/radv_query.c | 194 ++++++++++++++++++++++++--------------------
1 file changed, 107 insertions(+), 87 deletions(-)
diff --git a/src/amd/vulkan/radv_query.c b/src/amd/vulkan/radv_query.c
index 9fee4d2b491..56364f1a5a2 100644
--- a/src/amd/vulkan/radv_query.c
+++ b/src/amd/vulkan/radv_query.c
@@ -1087,7 +1087,6 @@ void radv_CmdBeginQuery(
RADV_FROM_HANDLE(radv_query_pool, pool, queryPool);
struct radeon_winsys_cs *cs = cmd_buffer->cs;
uint64_t va = radv_buffer_get_va(pool->bo);
- va += pool->stride * query;
radv_cs_add_buffer(cmd_buffer->device->ws, cs, pool->bo, 8);
@@ -1103,29 +1102,37 @@ void radv_CmdBeginQuery(
}
}
- switch (pool->type) {
- case VK_QUERY_TYPE_OCCLUSION:
- radeon_check_space(cmd_buffer->device->ws, cs, 7);
+ int num_querys = 1;
+ if (cmd_buffer->state.subpass && cmd_buffer->state.subpass->view_mask)
+ num_querys = util_bitcount(cmd_buffer->state.subpass->view_mask);
- ++cmd_buffer->state.active_occlusion_queries;
- if (cmd_buffer->state.active_occlusion_queries == 1)
- radv_set_db_count_control(cmd_buffer);
+ va += pool->stride * query;
+ for (unsigned i = 0; i < num_querys; i++) {
+ switch (pool->type) {
+ case VK_QUERY_TYPE_OCCLUSION:
+ radeon_check_space(cmd_buffer->device->ws, cs, 7);
- radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
- radeon_emit(cs, EVENT_TYPE(V_028A90_ZPASS_DONE) | EVENT_INDEX(1));
- radeon_emit(cs, va);
- radeon_emit(cs, va >> 32);
- break;
- case VK_QUERY_TYPE_PIPELINE_STATISTICS:
- radeon_check_space(cmd_buffer->device->ws, cs, 4);
+ ++cmd_buffer->state.active_occlusion_queries;
+ if (cmd_buffer->state.active_occlusion_queries == 1)
+ radv_set_db_count_control(cmd_buffer);
- radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
- radeon_emit(cs, EVENT_TYPE(V_028A90_SAMPLE_PIPELINESTAT) | EVENT_INDEX(2));
- radeon_emit(cs, va);
- radeon_emit(cs, va >> 32);
- break;
- default:
- unreachable("beginning unhandled query type");
+ radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
+ radeon_emit(cs, EVENT_TYPE(V_028A90_ZPASS_DONE) | EVENT_INDEX(1));
+ radeon_emit(cs, va);
+ radeon_emit(cs, va >> 32);
+ break;
+ case VK_QUERY_TYPE_PIPELINE_STATISTICS:
+ radeon_check_space(cmd_buffer->device->ws, cs, 4);
+
+ radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
+ radeon_emit(cs, EVENT_TYPE(V_028A90_SAMPLE_PIPELINESTAT) | EVENT_INDEX(2));
+ radeon_emit(cs, va);
+ radeon_emit(cs, va >> 32);
+ break;
+ default:
+ unreachable("beginning unhandled query type");
+ }
+ va += pool->stride;
}
}
@@ -1145,40 +1152,46 @@ void radv_CmdEndQuery(
/* Do not need to add the pool BO to the list because the query must
* currently be active, which means the BO is already in the list.
*/
+ int num_querys = 1;
+ if (cmd_buffer->state.subpass && cmd_buffer->state.subpass->view_mask)
+ num_querys = util_bitcount(cmd_buffer->state.subpass->view_mask);
- switch (pool->type) {
- case VK_QUERY_TYPE_OCCLUSION:
- radeon_check_space(cmd_buffer->device->ws, cs, 14);
-
- cmd_buffer->state.active_occlusion_queries--;
- if (cmd_buffer->state.active_occlusion_queries == 0)
- radv_set_db_count_control(cmd_buffer);
-
- radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
- radeon_emit(cs, EVENT_TYPE(V_028A90_ZPASS_DONE) | EVENT_INDEX(1));
- radeon_emit(cs, va + 8);
- radeon_emit(cs, (va + 8) >> 32);
-
- break;
- case VK_QUERY_TYPE_PIPELINE_STATISTICS:
- radeon_check_space(cmd_buffer->device->ws, cs, 16);
+ for (unsigned i = 0; i < num_querys; i++) {
+ switch (pool->type) {
+ case VK_QUERY_TYPE_OCCLUSION:
+ radeon_check_space(cmd_buffer->device->ws, cs, 14);
- va += pipelinestat_block_size;
+ cmd_buffer->state.active_occlusion_queries--;
+ if (cmd_buffer->state.active_occlusion_queries == 0)
+ radv_set_db_count_control(cmd_buffer);
- radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
- radeon_emit(cs, EVENT_TYPE(V_028A90_SAMPLE_PIPELINESTAT) | EVENT_INDEX(2));
- radeon_emit(cs, va);
- radeon_emit(cs, va >> 32);
+ radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
+ radeon_emit(cs, EVENT_TYPE(V_028A90_ZPASS_DONE) | EVENT_INDEX(1));
+ radeon_emit(cs, va + 8);
+ radeon_emit(cs, (va + 8) >> 32);
- si_cs_emit_write_event_eop(cs,
- false,
- cmd_buffer->device->physical_device->rad_info.chip_class,
- radv_cmd_buffer_uses_mec(cmd_buffer),
- V_028A90_BOTTOM_OF_PIPE_TS, 0,
- 1, avail_va, 0, 1);
- break;
- default:
- unreachable("ending unhandled query type");
+ break;
+ case VK_QUERY_TYPE_PIPELINE_STATISTICS:
+ radeon_check_space(cmd_buffer->device->ws, cs, 16);
+
+ va += pipelinestat_block_size;
+
+ radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
+ radeon_emit(cs, EVENT_TYPE(V_028A90_SAMPLE_PIPELINESTAT) | EVENT_INDEX(2));
+ radeon_emit(cs, va);
+ radeon_emit(cs, va >> 32);
+
+ si_cs_emit_write_event_eop(cs,
+ false,
+ cmd_buffer->device->physical_device->rad_info.chip_class,
+ radv_cmd_buffer_uses_mec(cmd_buffer),
+ V_028A90_BOTTOM_OF_PIPE_TS, 0,
+ 1, avail_va, 0, 1);
+ break;
+ default:
+ unreachable("ending unhandled query type");
+ }
+ va += pool->stride;
}
}
@@ -1198,42 +1211,49 @@ void radv_CmdWriteTimestamp(
radv_cs_add_buffer(cmd_buffer->device->ws, cs, pool->bo, 5);
- MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 28);
-
- switch(pipelineStage) {
- case VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT:
- radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
- radeon_emit(cs, COPY_DATA_COUNT_SEL | COPY_DATA_WR_CONFIRM |
- COPY_DATA_SRC_SEL(COPY_DATA_TIMESTAMP) |
- COPY_DATA_DST_SEL(V_370_MEM_ASYNC));
- radeon_emit(cs, 0);
- radeon_emit(cs, 0);
- radeon_emit(cs, query_va);
- radeon_emit(cs, query_va >> 32);
-
- radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
- radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
- S_370_WR_CONFIRM(1) |
- S_370_ENGINE_SEL(V_370_ME));
- radeon_emit(cs, avail_va);
- radeon_emit(cs, avail_va >> 32);
- radeon_emit(cs, 1);
- break;
- default:
- si_cs_emit_write_event_eop(cs,
- false,
- cmd_buffer->device->physical_device->rad_info.chip_class,
- mec,
- V_028A90_BOTTOM_OF_PIPE_TS, 0,
- 3, query_va, 0, 0);
- si_cs_emit_write_event_eop(cs,
- false,
- cmd_buffer->device->physical_device->rad_info.chip_class,
- mec,
- V_028A90_BOTTOM_OF_PIPE_TS, 0,
- 1, avail_va, 0, 1);
- break;
- }
+ int num_querys = 1;
+ if (cmd_buffer->state.subpass && cmd_buffer->state.subpass->view_mask)
+ num_querys = util_bitcount(cmd_buffer->state.subpass->view_mask);
+
+ MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 28 * num_querys);
+ for (unsigned i = 0; i < num_querys; i++) {
+ switch(pipelineStage) {
+ case VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT:
+ radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
+ radeon_emit(cs, COPY_DATA_COUNT_SEL | COPY_DATA_WR_CONFIRM |
+ COPY_DATA_SRC_SEL(COPY_DATA_TIMESTAMP) |
+ COPY_DATA_DST_SEL(V_370_MEM_ASYNC));
+ radeon_emit(cs, 0);
+ radeon_emit(cs, 0);
+ radeon_emit(cs, query_va);
+ radeon_emit(cs, query_va >> 32);
+
+ radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
+ radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
+ S_370_WR_CONFIRM(1) |
+ S_370_ENGINE_SEL(V_370_ME));
+ radeon_emit(cs, avail_va);
+ radeon_emit(cs, avail_va >> 32);
+ radeon_emit(cs, 1);
+ break;
+ default:
+ si_cs_emit_write_event_eop(cs,
+ false,
+ cmd_buffer->device->physical_device->rad_info.chip_class,
+ mec,
+ V_028A90_BOTTOM_OF_PIPE_TS, 0,
+ 3, query_va, 0, 0);
+ si_cs_emit_write_event_eop(cs,
+ false,
+ cmd_buffer->device->physical_device->rad_info.chip_class,
+ mec,
+ V_028A90_BOTTOM_OF_PIPE_TS, 0,
+ 1, avail_va, 0, 1);
+ break;
+ }
+ query_va += pool->stride;
+ avail_va += 4;
+ }
assert(cmd_buffer->cs->cdw <= cdw_max);
}
--
2.14.3
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