[Mesa-dev] [PATCH] radv: handle exporting view index to fragment shader.

[Dave Airlie]

From: Dave Airlie <airlied at redhat.com>

The fragment shader was trying to read this, but nothing
was exporting it from the vertex shader. This handles
it like the prim id export.

Fixes:
dEQP-VK.multiview.secondary_cmd_buffer.*
dEQP-VK.multiview.index.fragment_shader.*

Signed-off-by: Dave Airlie <airlied at redhat.com>
---
 src/amd/vulkan/radv_nir_to_llvm.c | 18 ++++++++++++++++--
 src/amd/vulkan/radv_pipeline.c    |  4 ++++
 src/amd/vulkan/radv_shader.h      |  2 ++
 src/amd/vulkan/radv_shader_info.c |  2 ++
 4 files changed, 24 insertions(+), 2 deletions(-)

diff --git a/src/amd/vulkan/radv_nir_to_llvm.c b/src/amd/vulkan/radv_nir_to_llvm.c
index cedcd38b3a2..e2e64463fae 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -2183,7 +2183,7 @@ radv_load_output(struct radv_shader_context *ctx, unsigned index, unsigned chan)
 
 static void
 handle_vs_outputs_post(struct radv_shader_context *ctx,
-		       bool export_prim_id,
+		       bool export_prim_id, bool export_layer_id,
 		       struct radv_vs_output_info *outinfo)
 {
 	uint32_t param_count = 0;
@@ -2363,6 +2363,18 @@ handle_vs_outputs_post(struct radv_shader_context *ctx,
 		outinfo->export_prim_id = true;
 	}
 
+	if (export_layer_id) {
+		LLVMValueRef values[4];
+
+		values[0] = layer_value;
+		for (unsigned j = 1; j < 4; j++)
+			values[j] = ctx->ac.f32_0;
+
+		radv_export_param(ctx, param_count, values, 0xf);
+
+		outinfo->vs_output_param_offset[VARYING_SLOT_LAYER] = param_count++;
+	}
+
 	outinfo->pos_exports = num_pos_exports;
 	outinfo->param_exports = param_count;
 }
@@ -2825,6 +2837,7 @@ handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
 			handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
 		else
 			handle_vs_outputs_post(ctx, ctx->options->key.vs.export_prim_id,
+					       ctx->options->key.vs.export_layer_id,
 					       &ctx->shader_info->vs.outinfo);
 		break;
 	case MESA_SHADER_FRAGMENT:
@@ -2841,6 +2854,7 @@ handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
 			handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
 		else
 			handle_vs_outputs_post(ctx, ctx->options->key.tes.export_prim_id,
+					       ctx->options->key.tes.export_layer_id,
 					       &ctx->shader_info->tes.outinfo);
 		break;
 	default:
@@ -3439,7 +3453,7 @@ ac_gs_copy_shader_emit(struct radv_shader_context *ctx)
 		}
 		idx += slot_inc;
 	}
-	handle_vs_outputs_post(ctx, false, &ctx->shader_info->vs.outinfo);
+	handle_vs_outputs_post(ctx, false, false, &ctx->shader_info->vs.outinfo);
 }
 
 void
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 52a6d23718e..89c5e699414 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -1718,8 +1718,12 @@ void radv_create_shaders(struct radv_pipeline *pipeline,
 		/* TODO: These are no longer used as keys we should refactor this */
 		keys[MESA_SHADER_VERTEX].vs.export_prim_id =
 		        pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.prim_id_input;
+		keys[MESA_SHADER_VERTEX].vs.export_layer_id =
+		        pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.layer_input;
 		keys[MESA_SHADER_TESS_EVAL].tes.export_prim_id =
 		        pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.prim_id_input;
+		keys[MESA_SHADER_TESS_EVAL].tes.export_layer_id =
+		        pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.layer_input;
 	}
 
 	if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_TESS_CTRL]) {
diff --git a/src/amd/vulkan/radv_shader.h b/src/amd/vulkan/radv_shader.h
index 40e92b52f38..ae30d6125b1 100644
--- a/src/amd/vulkan/radv_shader.h
+++ b/src/amd/vulkan/radv_shader.h
@@ -58,11 +58,13 @@ struct radv_vs_variant_key {
 	uint32_t as_es:1;
 	uint32_t as_ls:1;
 	uint32_t export_prim_id:1;
+	uint32_t export_layer_id:1;
 };
 
 struct radv_tes_variant_key {
 	uint32_t as_es:1;
 	uint32_t export_prim_id:1;
+	uint32_t export_layer_id:1;
 	uint8_t num_patches;
 	uint8_t tcs_num_outputs;
 };
diff --git a/src/amd/vulkan/radv_shader_info.c b/src/amd/vulkan/radv_shader_info.c
index ded3281516d..7208bd2f587 100644
--- a/src/amd/vulkan/radv_shader_info.c
+++ b/src/amd/vulkan/radv_shader_info.c
@@ -90,6 +90,8 @@ gather_intrinsic_info(const nir_shader *nir, const nir_intrinsic_instr *instr,
 		break;
 	case nir_intrinsic_load_view_index:
 		info->needs_multiview_view_index = true;
+		if (nir->info.stage == MESA_SHADER_FRAGMENT)
+			info->ps.layer_input = true;
 		break;
 	case nir_intrinsic_load_invocation_id:
 		info->uses_invocation_id = true;
-- 
2.14.3