[Mesa-dev] [PATCH 06/11] intel/compiler/icl: Clear "null render target" bit in extended message descriptor

[Kenneth Graunke]

On Wednesday, March 21, 2018 2:06:17 PM PDT Matt Turner wrote:
> From: Jason Ekstrand <jason.ekstrand at intel.com>
> 
> Otherwise all our render target writes go no where.
> ---
>  src/intel/compiler/brw_eu_emit.c | 3 +++
>  src/intel/compiler/brw_inst.h    | 3 +++
>  2 files changed, 6 insertions(+)
> 
> diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c
> index fe7fa8723e1..99c09e6f541 100644
> --- a/src/intel/compiler/brw_eu_emit.c
> +++ b/src/intel/compiler/brw_eu_emit.c
> @@ -536,6 +536,9 @@ brw_set_dp_write_message(struct brw_codegen *p,
>     if (devinfo->gen < 7) {
>        brw_inst_set_dp_write_commit(devinfo, insn, send_commit_msg);
>     }
> +
> +   if (devinfo->gen >= 11)
> +      brw_inst_set_null_rt(devinfo, insn, false);
>  }
>  
>  void
> diff --git a/src/intel/compiler/brw_inst.h b/src/intel/compiler/brw_inst.h
> index e6998973b64..b569e0e41b7 100644
> --- a/src/intel/compiler/brw_inst.h
> +++ b/src/intel/compiler/brw_inst.h
> @@ -505,6 +505,9 @@ FF(sfid,
>     /* 6:   */  27,  24,
>     /* 7:   */  27,  24,
>     /* 8:   */  27,  24)
> +FF(null_rt,
> +   /* 4-7: */ -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
> +   /* 8:   */ 80, 80)
>  FC(base_mrf,   27,  24, devinfo->gen < 6);
>  /** @} */
>  
> 

This bit is new on Gen11, so letting it slop through on Gen8+ seems
pretty lame.  But, updating all the macros to support Gen11+ only bits
also seems pretty lame.  Given that Curro's already reworking all the
message descriptor stuff, this will probably do for now.

With a comment saying something like /* actually only Gen11+ */,

Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
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