[Mesa-dev] [PATCH 5/5] ac/gpu_info: print GB_ADDR_CONFIG

[Marek Olšák]

From: Marek Olšák <marek.olsak at amd.com>

---
 src/amd/common/ac_gpu_info.c | 50 ++++++++++++++++++++++++++++++++++++++++++++
 src/amd/common/ac_gpu_info.h |  1 +
 2 files changed, 51 insertions(+)

diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index 9fe1a318723..bd7bc50dafb 100644
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -315,20 +315,21 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
 	info->has_ctx_priority = info->drm_minor >= 22;
 	/* TODO: Enable this once the kernel handles it efficiently. */
 	/*info->has_local_buffers = ws->info.drm_minor >= 20;*/
 	info->num_render_backends = amdinfo->rb_pipes;
 	info->clock_crystal_freq = amdinfo->gpu_counter_freq;
 	if (!info->clock_crystal_freq) {
 		fprintf(stderr, "amdgpu: clock crystal frequency is 0, timestamps will be wrong\n");
 		info->clock_crystal_freq = 1;
 	}
 	info->tcc_cache_line_size = 64; /* TC L2 line size on GCN */
+	info->gb_addr_config = amdinfo->gb_addr_cfg;
 	if (info->chip_class == GFX9) {
 		info->num_tile_pipes = 1 << G_0098F8_NUM_PIPES(amdinfo->gb_addr_cfg);
 		info->pipe_interleave_bytes =
 			256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX9(amdinfo->gb_addr_cfg);
 	} else {
 		info->num_tile_pipes = cik_get_num_tile_pipes(amdinfo);
 		info->pipe_interleave_bytes =
 			256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX6(amdinfo->gb_addr_cfg);
 	}
 	info->r600_has_virtual_memory = true;
@@ -462,11 +463,60 @@ void ac_print_gpu_info(struct radeon_info *info)
 	printf("    num_good_compute_units = %i\n", info->num_good_compute_units);
 	printf("    max_se = %i\n", info->max_se);
 	printf("    max_sh_per_se = %i\n", info->max_sh_per_se);
 
 	printf("Render backend info:\n");
 	printf("    num_render_backends = %i\n", info->num_render_backends);
 	printf("    num_tile_pipes = %i\n", info->num_tile_pipes);
 	printf("    pipe_interleave_bytes = %i\n", info->pipe_interleave_bytes);
 	printf("    enabled_rb_mask = 0x%x\n", info->enabled_rb_mask);
 	printf("    max_alignment = %u\n", (unsigned)info->max_alignment);
+
+	printf("GB_ADDR_CONFIG:\n");
+	if (info->chip_class >= GFX9) {
+		printf("    num_pipes = %u\n",
+		       1 << G_0098F8_NUM_PIPES(info->gb_addr_config));
+		printf("    pipe_interleave_size = %u\n",
+		       256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX9(info->gb_addr_config));
+		printf("    max_compressed_frags = %u\n",
+		       1 << G_0098F8_MAX_COMPRESSED_FRAGS(info->gb_addr_config));
+		printf("    bank_interleave_size = %u\n",
+		       1 << G_0098F8_BANK_INTERLEAVE_SIZE(info->gb_addr_config));
+		printf("    num_banks = %u\n",
+		       1 << G_0098F8_NUM_BANKS(info->gb_addr_config));
+		printf("    shader_engine_tile_size = %u\n",
+		       16 << G_0098F8_SHADER_ENGINE_TILE_SIZE(info->gb_addr_config));
+		printf("    num_shader_engines = %u\n",
+		       1 << G_0098F8_NUM_SHADER_ENGINES_GFX9(info->gb_addr_config));
+		printf("    num_gpus = %u (raw)\n",
+		       G_0098F8_NUM_GPUS_GFX9(info->gb_addr_config));
+		printf("    multi_gpu_tile_size = %u (raw)\n",
+		       G_0098F8_MULTI_GPU_TILE_SIZE(info->gb_addr_config));
+		printf("    num_rb_per_se = %u\n",
+		       1 << G_0098F8_NUM_RB_PER_SE(info->gb_addr_config));
+		printf("    row_size = %u\n",
+		       1024 << G_0098F8_ROW_SIZE(info->gb_addr_config));
+		printf("    num_lower_pipes = %u (raw)\n",
+		       G_0098F8_NUM_LOWER_PIPES(info->gb_addr_config));
+		printf("    se_enable = %u (raw)\n",
+		       G_0098F8_SE_ENABLE(info->gb_addr_config));
+	} else {
+		printf("    num_pipes = %u\n",
+		       1 << G_0098F8_NUM_PIPES(info->gb_addr_config));
+		printf("    pipe_interleave_size = %u\n",
+		       256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX6(info->gb_addr_config));
+		printf("    bank_interleave_size = %u\n",
+		       1 << G_0098F8_BANK_INTERLEAVE_SIZE(info->gb_addr_config));
+		printf("    num_shader_engines = %u\n",
+		       1 << G_0098F8_NUM_SHADER_ENGINES_GFX6(info->gb_addr_config));
+		printf("    shader_engine_tile_size = %u\n",
+		       16 << G_0098F8_SHADER_ENGINE_TILE_SIZE(info->gb_addr_config));
+		printf("    num_gpus = %u (raw)\n",
+		       G_0098F8_NUM_GPUS_GFX6(info->gb_addr_config));
+		printf("    multi_gpu_tile_size = %u (raw)\n",
+		       G_0098F8_MULTI_GPU_TILE_SIZE(info->gb_addr_config));
+		printf("    row_size = %u\n",
+		       1024 << G_0098F8_ROW_SIZE(info->gb_addr_config));
+		printf("    num_lower_pipes = %u (raw)\n",
+		       G_0098F8_NUM_LOWER_PIPES(info->gb_addr_config));
+	}
 }
diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h
index 8aad678797c..75cb98020d2 100644
--- a/src/amd/common/ac_gpu_info.h
+++ b/src/amd/common/ac_gpu_info.h
@@ -103,20 +103,21 @@ struct radeon_info {
 	uint32_t                    num_good_compute_units;
 	uint32_t                    max_se; /* shader engines */
 	uint32_t                    max_sh_per_se; /* shader arrays per shader engine */
 
 	/* Render backends (color + depth blocks). */
 	uint32_t                    r300_num_gb_pipes;
 	uint32_t                    r300_num_z_pipes;
 	uint32_t                    r600_gb_backend_map; /* R600 harvest config */
 	bool                        r600_gb_backend_map_valid;
 	uint32_t                    r600_num_banks;
+	uint32_t                    gb_addr_config;
 	uint32_t                    num_render_backends;
 	uint32_t                    num_tile_pipes; /* pipe count from PIPE_CONFIG */
 	uint32_t                    pipe_interleave_bytes;
 	uint32_t                    enabled_rb_mask; /* GCN harvest config */
 	uint64_t                    max_alignment; /* from addrlib */
 
 	/* Tile modes. */
 	uint32_t                    si_tile_mode_array[32];
 	uint32_t                    cik_macrotile_mode_array[16];
 };
-- 
2.15.1