[Mesa-dev] [PATCH] i965: Drop PIPE_CONTROL_NO_WRITE from various calls.

[Lionel Landwerlin]

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>

On 22/03/18 18:22, Kenneth Graunke wrote:
> This is just zero - passing nothing already gives us a post-sync
> operation of "nothing".
> ---
>   src/mesa/drivers/dri/i965/brw_misc_state.c   | 4 +---
>   src/mesa/drivers/dri/i965/brw_pipe_control.c | 2 +-
>   src/mesa/drivers/dri/i965/brw_program.c      | 4 +---
>   src/mesa/drivers/dri/i965/gen7_l3_state.c    | 5 +----
>   4 files changed, 4 insertions(+), 11 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c
> index 29d74876c27..05517ebf587 100644
> --- a/src/mesa/drivers/dri/i965/brw_misc_state.c
> +++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
> @@ -462,15 +462,13 @@ brw_emit_select_pipeline(struct brw_context *brw, enum brw_pipeline pipeline)
>                                     PIPE_CONTROL_RENDER_TARGET_FLUSH |
>                                     PIPE_CONTROL_DEPTH_CACHE_FLUSH |
>                                     dc_flush |
> -                                  PIPE_CONTROL_NO_WRITE |
>                                     PIPE_CONTROL_CS_STALL);
>   
>         brw_emit_pipe_control_flush(brw,
>                                     PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
>                                     PIPE_CONTROL_CONST_CACHE_INVALIDATE |
>                                     PIPE_CONTROL_STATE_CACHE_INVALIDATE |
> -                                  PIPE_CONTROL_INSTRUCTION_INVALIDATE |
> -                                  PIPE_CONTROL_NO_WRITE);
> +                                  PIPE_CONTROL_INSTRUCTION_INVALIDATE);
>   
>      } else {
>         /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
> diff --git a/src/mesa/drivers/dri/i965/brw_pipe_control.c b/src/mesa/drivers/dri/i965/brw_pipe_control.c
> index 2350a6148f3..71f79b18474 100644
> --- a/src/mesa/drivers/dri/i965/brw_pipe_control.c
> +++ b/src/mesa/drivers/dri/i965/brw_pipe_control.c
> @@ -547,7 +547,7 @@ brw_emit_mi_flush(struct brw_context *brw)
>            OUT_BATCH(0);
>         ADVANCE_BATCH();
>      } else {
> -      int flags = PIPE_CONTROL_NO_WRITE | PIPE_CONTROL_RENDER_TARGET_FLUSH;
> +      int flags = PIPE_CONTROL_RENDER_TARGET_FLUSH;
>         if (devinfo->gen >= 6) {
>            flags |= PIPE_CONTROL_INSTRUCTION_INVALIDATE |
>                     PIPE_CONTROL_CONST_CACHE_INVALIDATE |
> diff --git a/src/mesa/drivers/dri/i965/brw_program.c b/src/mesa/drivers/dri/i965/brw_program.c
> index 4ba46a3c826..23743639dc8 100644
> --- a/src/mesa/drivers/dri/i965/brw_program.c
> +++ b/src/mesa/drivers/dri/i965/brw_program.c
> @@ -277,9 +277,7 @@ brw_memory_barrier(struct gl_context *ctx, GLbitfield barriers)
>   {
>      struct brw_context *brw = brw_context(ctx);
>      const struct gen_device_info *devinfo = &brw->screen->devinfo;
> -   unsigned bits = (PIPE_CONTROL_DATA_CACHE_FLUSH |
> -                    PIPE_CONTROL_NO_WRITE |
> -                    PIPE_CONTROL_CS_STALL);
> +   unsigned bits = PIPE_CONTROL_DATA_CACHE_FLUSH | PIPE_CONTROL_CS_STALL;
>      assert(devinfo->gen >= 7 && devinfo->gen <= 11);
>   
>      if (barriers & (GL_VERTEX_ATTRIB_ARRAY_BARRIER_BIT |
> diff --git a/src/mesa/drivers/dri/i965/gen7_l3_state.c b/src/mesa/drivers/dri/i965/gen7_l3_state.c
> index 8c8f4169e7e..8c6c4c47481 100644
> --- a/src/mesa/drivers/dri/i965/gen7_l3_state.c
> +++ b/src/mesa/drivers/dri/i965/gen7_l3_state.c
> @@ -86,7 +86,6 @@ setup_l3_config(struct brw_context *brw, const struct gen_l3_config *cfg)
>       */
>      brw_emit_pipe_control_flush(brw,
>                                  PIPE_CONTROL_DATA_CACHE_FLUSH |
> -                               PIPE_CONTROL_NO_WRITE |
>                                  PIPE_CONTROL_CS_STALL);
>   
>      /* ...followed by a second pipelined PIPE_CONTROL that initiates
> @@ -107,15 +106,13 @@ setup_l3_config(struct brw_context *brw, const struct gen_l3_config *cfg)
>                                  PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
>                                  PIPE_CONTROL_CONST_CACHE_INVALIDATE |
>                                  PIPE_CONTROL_INSTRUCTION_INVALIDATE |
> -                               PIPE_CONTROL_STATE_CACHE_INVALIDATE |
> -                               PIPE_CONTROL_NO_WRITE);
> +                               PIPE_CONTROL_STATE_CACHE_INVALIDATE);
>   
>      /* Now send a third stalling flush to make sure that invalidation is
>       * complete when the L3 configuration registers are modified.
>       */
>      brw_emit_pipe_control_flush(brw,
>                                  PIPE_CONTROL_DATA_CACHE_FLUSH |
> -                               PIPE_CONTROL_NO_WRITE |
>                                  PIPE_CONTROL_CS_STALL);
>   
>      if (devinfo->gen >= 8) {