[Mesa-dev] [PATCH 1/2] radv: add support for VK_EXT_sampler_filter_minmax

[Samuel Pitoiset]

The driver only supports the required formats for now.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
---
 src/amd/vulkan/radv_device.c  | 35 ++++++++++++++++++++++++++++++++++-
 src/amd/vulkan/radv_formats.c | 36 ++++++++++++++++++++++++++++++++++++
 2 files changed, 70 insertions(+), 1 deletion(-)

diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 9c82fd059f..5eeff1da22 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -44,6 +44,7 @@
 #include "vk_format.h"
 #include "sid.h"
 #include "gfx9d.h"
+#include "addrlib/gfx9/chip/gfx9_enum.h"
 #include "util/debug.h"
 
 static int
@@ -943,6 +944,14 @@ void radv_GetPhysicalDeviceProperties2(
 			properties->maxMemoryAllocationSize = 0xFFFFFFFFull;
 			break;
 		}
+		case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES_EXT: {
+			VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *properties =
+				(VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *)ext;
+			/* GFX6-8 only support single channel min/max filter. */
+			properties->filterMinmaxImageComponentMapping = pdevice->rad_info.chip_class >= GFX9;
+			properties->filterMinmaxSingleComponentFormats = true;
+			break;
+		}
 		default:
 			break;
 		}
@@ -3962,6 +3971,22 @@ radv_tex_aniso_filter(unsigned filter)
 	return 4;
 }
 
+static unsigned
+radv_tex_filter_mode(VkSamplerReductionModeEXT mode)
+{
+	switch (mode) {
+	case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT:
+		return SQ_IMG_FILTER_MODE_BLEND;
+	case VK_SAMPLER_REDUCTION_MODE_MIN_EXT:
+		return SQ_IMG_FILTER_MODE_MIN;
+	case VK_SAMPLER_REDUCTION_MODE_MAX_EXT:
+		return SQ_IMG_FILTER_MODE_MAX;
+	default:
+		break;
+	}
+	return 0;
+}
+
 static void
 radv_init_sampler(struct radv_device *device,
 		  struct radv_sampler *sampler,
@@ -3971,6 +3996,13 @@ radv_init_sampler(struct radv_device *device,
 					(uint32_t) pCreateInfo->maxAnisotropy : 0;
 	uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
 	bool is_vi = (device->physical_device->rad_info.chip_class >= VI);
+	unsigned filter_mode = SQ_IMG_FILTER_MODE_BLEND;
+
+	const struct VkSamplerReductionModeCreateInfoEXT *sampler_reduction =
+		vk_find_struct_const(pCreateInfo->pNext,
+				     SAMPLER_REDUCTION_MODE_CREATE_INFO_EXT);
+	if (sampler_reduction)
+		filter_mode = radv_tex_filter_mode(sampler_reduction->reductionMode);
 
 	sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
 			     S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
@@ -3981,7 +4013,8 @@ radv_init_sampler(struct radv_device *device,
 			     S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
 			     S_008F30_ANISO_BIAS(max_aniso_ratio) |
 			     S_008F30_DISABLE_CUBE_WRAP(0) |
-			     S_008F30_COMPAT_MODE(is_vi));
+			     S_008F30_COMPAT_MODE(is_vi) |
+			     S_008F30_FILTER_MODE(filter_mode));
 	sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
 			     S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
 			     S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
diff --git a/src/amd/vulkan/radv_formats.c b/src/amd/vulkan/radv_formats.c
index da341a3a84..efb1d78790 100644
--- a/src/amd/vulkan/radv_formats.c
+++ b/src/amd/vulkan/radv_formats.c
@@ -541,6 +541,35 @@ static bool radv_is_zs_format_supported(VkFormat format)
 	return radv_translate_dbformat(format) != V_028040_Z_INVALID || format == VK_FORMAT_S8_UINT;
 }
 
+static bool radv_is_filter_minmax_format_supported(VkFormat format)
+{
+	/* From the Vulkan spec 1.1.71:
+	 *
+	 * "The following formats must support the
+	 *  VK_FORMAT_FEATURE_SAMPLED_IMAGE_FILTER_MINMAX_BIT_EXT feature with
+	 *  VK_IMAGE_TILING_OPTIMAL, if they support
+	 *  VK_FORMAT_FEATURE_SAMPLED_IMAGE_BIT."
+	 */
+	/* TODO: enable more formats. */
+	switch (format) {
+	case VK_FORMAT_R8_UNORM:
+	case VK_FORMAT_R8_SNORM:
+	case VK_FORMAT_R16_UNORM:
+	case VK_FORMAT_R16_SNORM:
+	case VK_FORMAT_R16_SFLOAT:
+	case VK_FORMAT_R32_SFLOAT:
+	case VK_FORMAT_D16_UNORM:
+	case VK_FORMAT_X8_D24_UNORM_PACK32:
+	case VK_FORMAT_D32_SFLOAT:
+	case VK_FORMAT_D16_UNORM_S8_UINT:
+	case VK_FORMAT_D24_UNORM_S8_UINT:
+	case VK_FORMAT_D32_SFLOAT_S8_UINT:
+		return true;
+	default:
+		return false;
+	}
+}
+
 static void
 radv_physical_device_get_format_properties(struct radv_physical_device *physical_device,
 					   VkFormat format,
@@ -578,6 +607,9 @@ radv_physical_device_get_format_properties(struct radv_physical_device *physical
 			tiled |= VK_FORMAT_FEATURE_TRANSFER_SRC_BIT_KHR |
 			         VK_FORMAT_FEATURE_TRANSFER_DST_BIT_KHR;
 
+			if (radv_is_filter_minmax_format_supported(format))
+				 tiled |= VK_FORMAT_FEATURE_SAMPLED_IMAGE_FILTER_MINMAX_BIT_EXT;
+
 			/* GFX9 doesn't support linear depth surfaces */
 			if (physical_device->rad_info.chip_class >= GFX9)
 				linear = 0;
@@ -589,6 +621,10 @@ radv_physical_device_get_format_properties(struct radv_physical_device *physical
 				VK_FORMAT_FEATURE_BLIT_SRC_BIT;
 			tiled |= VK_FORMAT_FEATURE_SAMPLED_IMAGE_BIT |
 				VK_FORMAT_FEATURE_BLIT_SRC_BIT;
+
+			if (radv_is_filter_minmax_format_supported(format))
+				 tiled |= VK_FORMAT_FEATURE_SAMPLED_IMAGE_FILTER_MINMAX_BIT_EXT;
+
 			if (linear_sampling) {
 				linear |= VK_FORMAT_FEATURE_SAMPLED_IMAGE_FILTER_LINEAR_BIT;
 				tiled |= VK_FORMAT_FEATURE_SAMPLED_IMAGE_FILTER_LINEAR_BIT;
-- 
2.16.2