[Mesa-dev] [PATCH 14/16] radeonsi: set DB_EQAA the same as Vulkan

[Marek Olšák]

From: Marek Olšák <marek.olsak at amd.com>

These never change, but they only affect EQAA, which isn't implemented.
---
 src/gallium/drivers/radeonsi/si_state.c | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index b50182582c6..62d0ed99d94 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -3314,20 +3314,24 @@ static void si_emit_msaa_config(struct si_context *sctx)
 		S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
 		S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast) |
 		S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
 		/* always 1: */
 		S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
 		S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
 		S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
 		S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
 		S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
 		S_028A4C_FORCE_EOV_REZ_ENABLE(1);
+	unsigned db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
+			   S_028804_INCOHERENT_EQAA_READS(1) |
+			   S_028804_INTERPOLATE_COMP_Z(1) |
+			   S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
 
 	int setup_samples = sctx->framebuffer.nr_samples > 1 ? sctx->framebuffer.nr_samples :
 			    sctx->smoothing_enabled ? SI_NUM_SMOOTH_AA_SAMPLES : 0;
 
 	/* Required by OpenGL line rasterization.
 	 *
 	 * TODO: We should also enable perpendicular endcaps for AA lines,
 	 *       but that requires implementing line stippling in the pixel
 	 *       shader. SC can only do line stippling with axis-aligned
 	 *       endcaps.
@@ -3350,45 +3354,41 @@ static void si_emit_msaa_config(struct si_context *sctx)
 
 		radeon_set_context_reg_seq(cs, R_028BDC_PA_SC_LINE_CNTL, 2);
 		radeon_emit(cs, sc_line_cntl |
 			    S_028BDC_EXPAND_LINE_WIDTH(1)); /* R_028BDC_PA_SC_LINE_CNTL */
 		radeon_emit(cs, S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
 			    S_028BE0_MAX_SAMPLE_DIST(max_dist[log_samples]) |
 			    S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples)); /* R_028BE0_PA_SC_AA_CONFIG */
 
 		if (sctx->framebuffer.nr_samples > 1) {
 			radeon_set_context_reg(cs, R_028804_DB_EQAA,
+					       db_eqaa |
 					       S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
 					       S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
 					       S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
-					       S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples) |
-					       S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
-					       S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
+					       S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples));
 			radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1,
 					       S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1) |
 					       sc_mode_cntl_1);
 		} else if (sctx->smoothing_enabled) {
 			radeon_set_context_reg(cs, R_028804_DB_EQAA,
-					       S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
-					       S_028804_STATIC_ANCHOR_ASSOCIATIONS(1) |
+					       db_eqaa |
 					       S_028804_OVERRASTERIZATION_AMOUNT(log_samples));
 			radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1,
 					       sc_mode_cntl_1);
 		}
 	} else {
 		radeon_set_context_reg_seq(cs, R_028BDC_PA_SC_LINE_CNTL, 2);
 		radeon_emit(cs, sc_line_cntl); /* R_028BDC_PA_SC_LINE_CNTL */
 		radeon_emit(cs, 0); /* R_028BE0_PA_SC_AA_CONFIG */
 
-		radeon_set_context_reg(cs, R_028804_DB_EQAA,
-				       S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
-				       S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
+		radeon_set_context_reg(cs, R_028804_DB_EQAA, db_eqaa);
 		radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1,
 				       sc_mode_cntl_1);
 	}
 
 	/* GFX9: Flush DFSM when the AA mode changes. */
 	if (sctx->screen->dfsm_allowed) {
 		radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
 		radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
 	}
 }
-- 
2.17.0