[Mesa-dev] [PATCH 8/9] radeonsi: set up EQAA image descriptors properly
Marek Olšák
maraeo at gmail.com
Wed May 2 04:13:24 UTC 2018
From: Marek Olšák <marek.olsak at amd.com>
---
src/gallium/drivers/radeonsi/si_state.c | 96 ++++++++++++++++++++-----
1 file changed, 80 insertions(+), 16 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index fce796f7543..e133bf28589 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -3594,25 +3594,28 @@ si_make_texture_descriptor(struct si_screen *screen,
unsigned first_level, unsigned last_level,
unsigned first_layer, unsigned last_layer,
unsigned width, unsigned height, unsigned depth,
uint32_t *state,
uint32_t *fmask_state)
{
struct pipe_resource *res = &tex->buffer.b.b;
const struct util_format_description *desc;
unsigned char swizzle[4];
int first_non_void;
- unsigned num_format, data_format, type;
+ unsigned num_format, data_format, type, num_samples;
uint64_t va;
desc = util_format_description(pipe_format);
+ num_samples = desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS ?
+ MAX2(1, res->nr_samples) : tex->num_color_samples;
+
if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
const unsigned char swizzle_wwww[4] = {3, 3, 3, 3};
switch (pipe_format) {
case PIPE_FORMAT_S8_UINT_Z24_UNORM:
case PIPE_FORMAT_X32_S8X24_UINT:
case PIPE_FORMAT_X8Z24_UNORM:
util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
@@ -3721,21 +3724,21 @@ si_make_texture_descriptor(struct si_screen *screen,
res->target == PIPE_TEXTURE_3D))) {
/* For the purpose of shader images, treat cube maps and 3D
* textures as 2D arrays. For 3D textures, the address
* calculations for mipmaps are different, so we rely on the
* caller to effectively disable mipmaps.
*/
type = V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
assert(res->target != PIPE_TEXTURE_3D || (first_level == 0 && last_level == 0));
} else {
- type = si_tex_dim(screen, tex, target, res->nr_samples);
+ type = si_tex_dim(screen, tex, target, num_samples);
}
if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
height = 1;
depth = res->array_size;
} else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
if (sampler || res->target != PIPE_TEXTURE_3D)
depth = res->array_size;
} else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
@@ -3744,45 +3747,44 @@ si_make_texture_descriptor(struct si_screen *screen,
state[0] = 0;
state[1] = (S_008F14_DATA_FORMAT_GFX6(data_format) |
S_008F14_NUM_FORMAT_GFX6(num_format));
state[2] = (S_008F18_WIDTH(width - 1) |
S_008F18_HEIGHT(height - 1) |
S_008F18_PERF_MOD(4));
state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
- S_008F1C_BASE_LEVEL(res->nr_samples > 1 ?
- 0 : first_level) |
- S_008F1C_LAST_LEVEL(res->nr_samples > 1 ?
- util_logbase2(res->nr_samples) :
+ S_008F1C_BASE_LEVEL(num_samples > 1 ? 0 : first_level) |
+ S_008F1C_LAST_LEVEL(num_samples > 1 ?
+ util_logbase2(num_samples) :
last_level) |
S_008F1C_TYPE(type));
state[4] = 0;
state[5] = S_008F24_BASE_ARRAY(first_layer);
state[6] = 0;
state[7] = 0;
if (screen->info.chip_class >= GFX9) {
unsigned bc_swizzle = gfx9_border_color_swizzle(desc->swizzle);
/* Depth is the the last accessible layer on Gfx9.
* The hw doesn't need to know the total number of layers.
*/
if (type == V_008F1C_SQ_RSRC_IMG_3D)
state[4] |= S_008F20_DEPTH(depth - 1);
else
state[4] |= S_008F20_DEPTH(last_layer);
state[4] |= S_008F20_BC_SWIZZLE(bc_swizzle);
- state[5] |= S_008F24_MAX_MIP(res->nr_samples > 1 ?
- util_logbase2(res->nr_samples) :
+ state[5] |= S_008F24_MAX_MIP(num_samples > 1 ?
+ util_logbase2(num_samples) :
tex->buffer.b.b.last_level);
} else {
state[3] |= S_008F1C_POW2_PAD(res->last_level > 0);
state[4] |= S_008F20_DEPTH(depth - 1);
state[5] |= S_008F24_LAST_ARRAY(last_layer);
}
if (tex->dcc_offset) {
state[6] = S_008F28_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(pipe_format));
} else {
@@ -3796,51 +3798,113 @@ si_make_texture_descriptor(struct si_screen *screen,
state[7] = 0xffffffff;
}
}
/* Initialize the sampler view for FMASK. */
if (tex->surface.fmask_size) {
uint32_t data_format, num_format;
va = tex->buffer.gpu_address + tex->fmask_offset;
+#define FMASK(s,f) (((unsigned)(s) * 16) + (f))
if (screen->info.chip_class >= GFX9) {
data_format = V_008F14_IMG_DATA_FORMAT_FMASK;
- switch (res->nr_samples) {
- case 2:
+ switch (FMASK(res->nr_samples, tex->num_color_samples)) {
+ case FMASK(2,1):
+ num_format = V_008F14_IMG_FMASK_8_2_1;
+ break;
+ case FMASK(2,2):
num_format = V_008F14_IMG_FMASK_8_2_2;
break;
- case 4:
+ case FMASK(4,1):
+ num_format = V_008F14_IMG_FMASK_8_4_1;
+ break;
+ case FMASK(4,2):
+ num_format = V_008F14_IMG_FMASK_8_4_2;
+ break;
+ case FMASK(4,4):
num_format = V_008F14_IMG_FMASK_8_4_4;
break;
- case 8:
+ case FMASK(8,1):
+ num_format = V_008F14_IMG_FMASK_8_8_1;
+ break;
+ case FMASK(8,2):
+ num_format = V_008F14_IMG_FMASK_16_8_2;
+ break;
+ case FMASK(8,4):
+ num_format = V_008F14_IMG_FMASK_32_8_4;
+ break;
+ case FMASK(8,8):
num_format = V_008F14_IMG_FMASK_32_8_8;
break;
+ case FMASK(16,1):
+ num_format = V_008F14_IMG_FMASK_16_16_1;
+ break;
+ case FMASK(16,2):
+ num_format = V_008F14_IMG_FMASK_32_16_2;
+ break;
+ case FMASK(16,4):
+ num_format = V_008F14_IMG_FMASK_64_16_4;
+ break;
+ case FMASK(16,8):
+ num_format = V_008F14_IMG_FMASK_64_16_8;
+ break;
default:
unreachable("invalid nr_samples");
}
} else {
- switch (res->nr_samples) {
- case 2:
+ switch (FMASK(res->nr_samples, tex->num_color_samples)) {
+ case FMASK(2,1):
+ data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F1;
+ break;
+ case FMASK(2,2):
data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
break;
- case 4:
+ case FMASK(4,1):
+ data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F1;
+ break;
+ case FMASK(4,2):
+ data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F2;
+ break;
+ case FMASK(4,4):
data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
break;
- case 8:
+ case FMASK(8,1):
+ data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S8_F1;
+ break;
+ case FMASK(8,2):
+ data_format = V_008F14_IMG_DATA_FORMAT_FMASK16_S8_F2;
+ break;
+ case FMASK(8,4):
+ data_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F4;
+ break;
+ case FMASK(8,8):
data_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
break;
+ case FMASK(16,1):
+ data_format = V_008F14_IMG_DATA_FORMAT_FMASK16_S16_F1;
+ break;
+ case FMASK(16,2):
+ data_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S16_F2;
+ break;
+ case FMASK(16,4):
+ data_format = V_008F14_IMG_DATA_FORMAT_FMASK64_S16_F4;
+ break;
+ case FMASK(16,8):
+ data_format = V_008F14_IMG_DATA_FORMAT_FMASK64_S16_F8;
+ break;
default:
unreachable("invalid nr_samples");
}
num_format = V_008F14_IMG_NUM_FORMAT_UINT;
}
+#undef FMASK
fmask_state[0] = (va >> 8) | tex->surface.fmask_tile_swizzle;
fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
S_008F14_DATA_FORMAT_GFX6(data_format) |
S_008F14_NUM_FORMAT_GFX6(num_format);
fmask_state[2] = S_008F18_WIDTH(width - 1) |
S_008F18_HEIGHT(height - 1);
fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
--
2.17.0
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