[Mesa-dev] [PATCH v2] spirv: convert some operands for bitwise shift and bitwise ops to uint32

[Jason Ekstrand]

On Wed, May 2, 2018 at 1:10 AM, Samuel Iglesias Gonsálvez <
siglesias at igalia.com> wrote:

> SPIR-V allows to define the shift, offset and count operands for
> shift and bitfield opcodes with a bit-size different than 32 bits,
> but in NIR the opcodes have that limitation. As agreed in the
> mailing list, this patch adds a conversion to 32 bits to fix this.
>
> For more info, see:
>
> https://lists.freedesktop.org/archives/mesa-dev/2018-April/193026.html
>
> v2:
> - src_bit_size will have zero value for variable bit-size operands (Jason).
>
> Signed-off-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
> ---
>  src/compiler/spirv/vtn_alu.c | 34 ++++++++++++++++++++++++++++++++++
>  1 file changed, 34 insertions(+)
>
> diff --git a/src/compiler/spirv/vtn_alu.c b/src/compiler/spirv/vtn_alu.c
> index 3134849ba90..4b21aa9b8ab 100644
> --- a/src/compiler/spirv/vtn_alu.c
> +++ b/src/compiler/spirv/vtn_alu.c
> @@ -635,6 +635,40 @@ vtn_handle_alu(struct vtn_builder *b, SpvOp opcode,
>        break;
>     }
>
> +   case SpvOpBitFieldInsert:
> +   case SpvOpBitFieldSExtract:
> +   case SpvOpBitFieldUExtract:
> +   case SpvOpShiftLeftLogical:
> +   case SpvOpShiftRightArithmetic:
> +   case SpvOpShiftRightLogical: {
> +      bool swap;
> +      unsigned src_bit_size = glsl_get_bit_size(vtn_src[0]->type);
>

Maybe call this src0_bit_size?  With that,

Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>

Thanks for fixing this!


> +      unsigned dst_bit_size = glsl_get_bit_size(type);
> +      nir_op op = vtn_nir_alu_op_for_spirv_opcode(b, opcode, &swap,
> +                                                  src_bit_size,
> dst_bit_size);
> +
> +      assert (op == nir_op_ushr || op == nir_op_ishr || op == nir_op_ishl
> ||
> +              op == nir_op_bitfield_insert || op ==
> nir_op_ubitfield_extract ||
> +              op == nir_op_ibitfield_extract);
> +
> +      for (unsigned i = 0; i < nir_op_infos[op].num_inputs; i++) {
> +         src_bit_size = nir_alu_type_get_type_size(
> nir_op_infos[op].input_types[i]);
> +         if (src_bit_size == 0)
> +            continue;
> +         if (src_bit_size != src[i]->bit_size) {
> +            assert(src_bit_size == 32);
> +            /* Convert the Shift, Offset and Count  operands to 32 bits,
> which is the bitsize
> +             * supported by the NIR instructions. See discussion here:
> +             *
> +             * https://lists.freedesktop.org/
> archives/mesa-dev/2018-April/193026.html
> +             */
> +            src[i] = nir_u2u32(&b->nb, src[i]);
> +         }
> +      }
> +      val->ssa->def = nir_build_alu(&b->nb, op, src[0], src[1], src[2],
> src[3]);
> +      break;
> +   }
> +
>     default: {
>        bool swap;
>        unsigned src_bit_size = glsl_get_bit_size(vtn_src[0]->type);
> --
> 2.14.1
>
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