[Mesa-dev] [PATCH 14/14] ac/gpu_info: add has_read_registers_query
Marek Olšák
maraeo at gmail.com
Thu May 3 00:19:52 UTC 2018
From: Marek Olšák <marek.olsak at amd.com>
---
src/amd/common/ac_gpu_info.c | 2 ++
src/amd/common/ac_gpu_info.h | 1 +
src/gallium/drivers/radeonsi/si_debug.c | 5 ++---
src/gallium/winsys/radeon/drm/radeon_drm_winsys.c | 1 +
4 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index 99f1996b414..a02fb4e4dc4 100644
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -331,20 +331,21 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
/* SI doesn't support unaligned loads. */
info->has_unaligned_shader_loads = info->chip_class != SI;
/* Disable sparse mappings on SI due to VM faults in CP DMA. Enable them once
* these faults are mitigated in software.
* Disable sparse mappings on GFX9 due to hangs.
*/
info->has_sparse_vm_mappings =
info->chip_class >= CIK && info->chip_class <= VI &&
info->drm_minor >= 13;
info->has_2d_tiling = true;
+ info->has_read_registers_query = true;
info->num_render_backends = amdinfo->rb_pipes;
/* The value returned by the kernel driver was wrong. */
if (info->family == CHIP_KAVERI)
info->num_render_backends = 2;
info->clock_crystal_freq = amdinfo->gpu_counter_freq;
if (!info->clock_crystal_freq) {
fprintf(stderr, "amdgpu: clock crystal frequency is 0, timestamps will be wrong\n");
info->clock_crystal_freq = 1;
@@ -491,20 +492,21 @@ void ac_print_gpu_info(struct radeon_info *info)
printf(" has_bo_metadata = %u\n", info->has_bo_metadata);
printf(" has_gpu_reset_status_query = %u\n", info->has_gpu_reset_status_query);
printf(" has_gpu_reset_counter_query = %u\n", info->has_gpu_reset_counter_query);
printf(" has_eqaa_surface_allocator = %u\n", info->has_eqaa_surface_allocator);
printf(" has_format_bc1_through_bc7 = %u\n", info->has_format_bc1_through_bc7);
printf(" kernel_flushes_tc_l2_after_ib = %u\n", info->kernel_flushes_tc_l2_after_ib);
printf(" has_indirect_compute_dispatch = %u\n", info->has_indirect_compute_dispatch);
printf(" has_unaligned_shader_loads = %u\n", info->has_unaligned_shader_loads);
printf(" has_sparse_vm_mappings = %u\n", info->has_sparse_vm_mappings);
printf(" has_2d_tiling = %u\n", info->has_2d_tiling);
+ printf(" has_read_registers_query = %u\n", info->has_read_registers_query);
printf("Shader core info:\n");
printf(" max_shader_clock = %i\n", info->max_shader_clock);
printf(" num_good_compute_units = %i\n", info->num_good_compute_units);
printf(" max_se = %i\n", info->max_se);
printf(" max_sh_per_se = %i\n", info->max_sh_per_se);
printf("Render backend info:\n");
printf(" num_render_backends = %i\n", info->num_render_backends);
printf(" num_tile_pipes = %i\n", info->num_tile_pipes);
diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h
index fb44f7c8af4..1201d811361 100644
--- a/src/amd/common/ac_gpu_info.h
+++ b/src/amd/common/ac_gpu_info.h
@@ -102,20 +102,21 @@ struct radeon_info {
bool has_bo_metadata;
bool has_gpu_reset_status_query;
bool has_gpu_reset_counter_query;
bool has_eqaa_surface_allocator;
bool has_format_bc1_through_bc7;
bool kernel_flushes_tc_l2_after_ib;
bool has_indirect_compute_dispatch;
bool has_unaligned_shader_loads;
bool has_sparse_vm_mappings;
bool has_2d_tiling;
+ bool has_read_registers_query;
/* Shader cores. */
uint32_t r600_max_quad_pipes; /* wave size / 16 */
uint32_t max_shader_clock;
uint32_t num_good_compute_units;
uint32_t max_se; /* shader engines */
uint32_t max_sh_per_se; /* shader arrays per shader engine */
/* Render backends (color + depth blocks). */
uint32_t r300_num_gb_pipes;
diff --git a/src/gallium/drivers/radeonsi/si_debug.c b/src/gallium/drivers/radeonsi/si_debug.c
index b7d40db21cb..36cbb8866ed 100644
--- a/src/gallium/drivers/radeonsi/si_debug.c
+++ b/src/gallium/drivers/radeonsi/si_debug.c
@@ -287,23 +287,22 @@ static void si_dump_mmapped_reg(struct si_context *sctx, FILE *f,
{
struct radeon_winsys *ws = sctx->ws;
uint32_t value;
if (ws->read_registers(ws, offset, 1, &value))
ac_dump_reg(f, sctx->chip_class, offset, value, ~0);
}
static void si_dump_debug_registers(struct si_context *sctx, FILE *f)
{
- if (sctx->screen->info.drm_major == 2 &&
- sctx->screen->info.drm_minor < 42)
- return; /* no radeon support */
+ if (!sctx->screen->info.has_read_registers_query)
+ return;
fprintf(f, "Memory-mapped registers:\n");
si_dump_mmapped_reg(sctx, f, R_008010_GRBM_STATUS);
/* No other registers can be read on DRM < 3.1.0. */
if (sctx->screen->info.drm_major < 3 ||
sctx->screen->info.drm_minor < 1) {
fprintf(f, "\n");
return;
}
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
index f7f6cdfbf9e..0b5f4b612b7 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
@@ -547,20 +547,21 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws)
* that are used for indirect compute dispatches. */
ws->info.has_indirect_compute_dispatch = ws->info.chip_class == CIK ||
(ws->info.chip_class == SI &&
ws->info.drm_minor >= 45);
/* SI doesn't support unaligned loads. */
ws->info.has_unaligned_shader_loads = ws->info.chip_class == CIK &&
ws->info.drm_minor >= 50;
ws->info.has_sparse_vm_mappings = false;
/* 2D tiling on CIK is supported since DRM 2.35.0 */
ws->info.has_2d_tiling = ws->info.chip_class <= SI || ws->info.drm_minor >= 35;
+ ws->info.has_read_registers_query = ws->info.drm_minor >= 42;
ws->check_vm = strstr(debug_get_option("R600_DEBUG", ""), "check_vm") != NULL;
return true;
}
static void radeon_winsys_destroy(struct radeon_winsys *rws)
{
struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
--
2.17.0
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