[Mesa-dev] [PATCH 10/10] i965: Require softpin support for Cannonlake and later.

[Daniel Vetter]

On Fri, May 04, 2018 at 01:16:29AM -0700, Kenneth Graunke wrote:
> On Friday, May 4, 2018 12:39:12 AM PDT Chris Wilson wrote:
> > Quoting Kenneth Graunke (2018-05-04 08:34:07)
> > > On Thursday, May 3, 2018 11:53:24 PM PDT Chris Wilson wrote:
> > > > Quoting Kenneth Graunke (2018-05-04 02:12:40)
> > > > > This isn't strictly necessary, but anyone running Cannonlake will
> > > > > already have Kernel 4.5 or later, so there's no reason to support
> > > > > the relocation model on Gen10+.
> > > > 
> > > > /o\ gvt. Need I say more?
> > > > -Chris
> > > 
> > > Yes.  What's the deal with GVT?
> > 
> > Their current restrictions involve forcing the use of a 32b
> > aliasing-ppgtt. Not that they support cnl+ yet, so they might remember
> > to lift that restriction in time.
> > -Chris
> 
> Wow, that's really miserable.  So, we can't actually depend on real
> PPGTT existing?  Do you know if/when they might fix this?
> 
> This seriously wrecks a lot of my plans if we can't assume PPGTT
> and have to deal with relocations for all of eternity.  Jason and I
> have been planning on doing PPGTT-only drivers for months.  We figured
> that full PPGTT had been working since Gen8 and surely would be viable
> on anything modern.  If it weren't for enterprise kernels, I would have
> required this all the way back to Gen8 in a heartbeat.

softpin with aliasing ppgtt should still work, just thrash really badly.
It only stops working when there's something pinned at a given offset. It
only fails if there's something pinned there. A slightly evil plan would
be to try that, given the gvt some good motivation to implement ppgtt :-)
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch