[Mesa-dev] [PATCH 1/3] intel/compiler: make brw_reg_type_from_bit_size usable from other places

[Iago Toral Quiroga]

This was private to brw_fs_nir.cpp but we are going to need it soon in
brw_fs.cpp, so move it there and make it available to other files as we
do for other utility functions.
---
 src/intel/compiler/brw_fs.cpp     | 59 +++++++++++++++++++++++++++++++++++++++
 src/intel/compiler/brw_fs.h       |  4 +++
 src/intel/compiler/brw_fs_nir.cpp | 59 ---------------------------------------
 3 files changed, 63 insertions(+), 59 deletions(-)

diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index dcba4ee8068..458c534c9c7 100644
--- a/src/intel/compiler/brw_fs.cpp
+++ b/src/intel/compiler/brw_fs.cpp
@@ -900,6 +900,65 @@ fs_inst::size_read(int arg) const
    return 0;
 }
 
+/*
+ * Returns a type based on a reference_type (word, float, half-float) and a
+ * given bit_size.
+ *
+ * Reference BRW_REGISTER_TYPE are HF,F,DF,W,D,UW,UD.
+ *
+ * @FIXME: 64-bit return types are always DF on integer types to maintain
+ * compability with uses of DF previously to the introduction of int64
+ * support.
+ */
+brw_reg_type
+brw_reg_type_from_bit_size(const unsigned bit_size,
+                           const brw_reg_type reference_type)
+{
+   switch(reference_type) {
+   case BRW_REGISTER_TYPE_HF:
+   case BRW_REGISTER_TYPE_F:
+   case BRW_REGISTER_TYPE_DF:
+      switch(bit_size) {
+      case 16:
+         return BRW_REGISTER_TYPE_HF;
+      case 32:
+         return BRW_REGISTER_TYPE_F;
+      case 64:
+         return BRW_REGISTER_TYPE_DF;
+      default:
+         unreachable("Invalid bit size");
+      }
+   case BRW_REGISTER_TYPE_W:
+   case BRW_REGISTER_TYPE_D:
+   case BRW_REGISTER_TYPE_Q:
+      switch(bit_size) {
+      case 16:
+         return BRW_REGISTER_TYPE_W;
+      case 32:
+         return BRW_REGISTER_TYPE_D;
+      case 64:
+         return BRW_REGISTER_TYPE_Q;
+      default:
+         unreachable("Invalid bit size");
+      }
+   case BRW_REGISTER_TYPE_UW:
+   case BRW_REGISTER_TYPE_UD:
+   case BRW_REGISTER_TYPE_UQ:
+      switch(bit_size) {
+      case 16:
+         return BRW_REGISTER_TYPE_UW;
+      case 32:
+         return BRW_REGISTER_TYPE_UD;
+      case 64:
+         return BRW_REGISTER_TYPE_UQ;
+      default:
+         unreachable("Invalid bit size");
+      }
+   default:
+      unreachable("Unknown type");
+   }
+}
+
 namespace {
    /* Return the subset of flag registers that an instruction could
     * potentially read or write based on the execution controls and flag
diff --git a/src/intel/compiler/brw_fs.h b/src/intel/compiler/brw_fs.h
index e384db809dc..c4d5ebee239 100644
--- a/src/intel/compiler/brw_fs.h
+++ b/src/intel/compiler/brw_fs.h
@@ -525,4 +525,8 @@ fs_reg setup_imm_df(const brw::fs_builder &bld,
 enum brw_barycentric_mode brw_barycentric_mode(enum glsl_interp_mode mode,
                                                nir_intrinsic_op op);
 
+brw_reg_type
+brw_reg_type_from_bit_size(const unsigned bit_size,
+                           const brw_reg_type reference_type);
+
 #endif /* BRW_FS_H */
diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp
index 58ddc456bae..490fd4a0461 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -260,65 +260,6 @@ fs_visitor::nir_emit_system_values()
    }
 }
 
-/*
- * Returns a type based on a reference_type (word, float, half-float) and a
- * given bit_size.
- *
- * Reference BRW_REGISTER_TYPE are HF,F,DF,W,D,UW,UD.
- *
- * @FIXME: 64-bit return types are always DF on integer types to maintain
- * compability with uses of DF previously to the introduction of int64
- * support.
- */
-static brw_reg_type
-brw_reg_type_from_bit_size(const unsigned bit_size,
-                           const brw_reg_type reference_type)
-{
-   switch(reference_type) {
-   case BRW_REGISTER_TYPE_HF:
-   case BRW_REGISTER_TYPE_F:
-   case BRW_REGISTER_TYPE_DF:
-      switch(bit_size) {
-      case 16:
-         return BRW_REGISTER_TYPE_HF;
-      case 32:
-         return BRW_REGISTER_TYPE_F;
-      case 64:
-         return BRW_REGISTER_TYPE_DF;
-      default:
-         unreachable("Invalid bit size");
-      }
-   case BRW_REGISTER_TYPE_W:
-   case BRW_REGISTER_TYPE_D:
-   case BRW_REGISTER_TYPE_Q:
-      switch(bit_size) {
-      case 16:
-         return BRW_REGISTER_TYPE_W;
-      case 32:
-         return BRW_REGISTER_TYPE_D;
-      case 64:
-         return BRW_REGISTER_TYPE_Q;
-      default:
-         unreachable("Invalid bit size");
-      }
-   case BRW_REGISTER_TYPE_UW:
-   case BRW_REGISTER_TYPE_UD:
-   case BRW_REGISTER_TYPE_UQ:
-      switch(bit_size) {
-      case 16:
-         return BRW_REGISTER_TYPE_UW;
-      case 32:
-         return BRW_REGISTER_TYPE_UD;
-      case 64:
-         return BRW_REGISTER_TYPE_UQ;
-      default:
-         unreachable("Invalid bit size");
-      }
-   default:
-      unreachable("Unknown type");
-   }
-}
-
 void
 fs_visitor::nir_emit_impl(nir_function_impl *impl)
 {
-- 
2.14.1