[Mesa-dev] [PATCH] ac/surface: Don't assert that bpp is power of two.
Bas Nieuwenhuizen
bas at basnieuwenhuizen.nl
Tue May 15 19:32:18 UTC 2018
No, this is a vulkan issue, where we want to let apps create linear
RGB float surfaces. (AMDVLK exposes this too:
http://vulkan.gpuinfo.org/displayreport.php?id=3222#formats, see
R32G32B32_SFLOAT and friends) Vulkan has no conecept of staging
textures (or at least the app does not have to tell the driver).
Though I'm not so sure anymore my patch is the right one, since vulkan
apps can share these surfaces with other apps using the same GPU.
On Tue, May 15, 2018 at 9:25 PM, Marek Olšák <maraeo at gmail.com> wrote:
> Would this work for you instead?
> https://cgit.freedesktop.org/~mareko/mesa/commit/?h=user-stride&id=1fadff480e53fb691add602933c5d711d7e4b6e0
>
> Marek
>
> On Mon, May 14, 2018 at 5:10 PM, Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
> wrote:
>>
>> There are non-shared linear images too, and those don't
>> need the extra alignment at all.
>>
>> So just keep track of whether the image can be exported.
>>
>> Fixes: e361970ed73 "radv: Add support for IMG_DATA_FORMAT_32_32_32."
>> ---
>> src/amd/common/ac_surface.c | 10 ++++++----
>> 1 file changed, 6 insertions(+), 4 deletions(-)
>>
>> diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
>> index 9e742dc8a45..f6c4cd7db0f 100644
>> --- a/src/amd/common/ac_surface.c
>> +++ b/src/amd/common/ac_surface.c
>> @@ -281,7 +281,7 @@ static int surf_config_sanity(const struct
>> ac_surf_config *config,
>> static int gfx6_compute_level(ADDR_HANDLE addrlib,
>> const struct ac_surf_config *config,
>> struct radeon_surf *surf, bool is_stencil,
>> - unsigned level, bool compressed,
>> + unsigned level, bool compressed, bool
>> shareable,
>> ADDR_COMPUTE_SURFACE_INFO_INPUT
>> *AddrSurfInfoIn,
>> ADDR_COMPUTE_SURFACE_INFO_OUTPUT
>> *AddrSurfInfoOut,
>> ADDR_COMPUTE_DCCINFO_INPUT *AddrDccIn,
>> @@ -301,7 +301,7 @@ static int gfx6_compute_level(ADDR_HANDLE addrlib,
>> */
>> if (config->info.levels == 1 &&
>> AddrSurfInfoIn->tileMode == ADDR_TM_LINEAR_ALIGNED &&
>> - AddrSurfInfoIn->bpp) {
>> + AddrSurfInfoIn->bpp && shareable) {
>> unsigned alignment = 256 / (AddrSurfInfoIn->bpp / 8);
>>
>> assert(util_is_power_of_two_or_zero(AddrSurfInfoIn->bpp));
>> @@ -560,6 +560,7 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib,
>> {
>> unsigned level;
>> bool compressed;
>> + bool shareable;
>> ADDR_COMPUTE_SURFACE_INFO_INPUT AddrSurfInfoIn = {0};
>> ADDR_COMPUTE_SURFACE_INFO_OUTPUT AddrSurfInfoOut = {0};
>> ADDR_COMPUTE_DCCINFO_INPUT AddrDccIn = {0};
>> @@ -579,6 +580,7 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib,
>> AddrSurfInfoOut.pTileInfo = &AddrTileInfoOut;
>>
>> compressed = surf->blk_w == 4 && surf->blk_h == 4;
>> + shareable = (surf->flags & RADEON_SURF_SHAREABLE);
>>
>> /* MSAA requires 2D tiling. */
>> if (config->info.samples > 1)
>> @@ -773,7 +775,7 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib,
>> if (!only_stencil) {
>> for (level = 0; level < config->info.levels; level++) {
>> r = gfx6_compute_level(addrlib, config, surf,
>> false, level, compressed,
>> - &AddrSurfInfoIn,
>> &AddrSurfInfoOut,
>> + shareable, &AddrSurfInfoIn,
>> &AddrSurfInfoOut,
>> &AddrDccIn, &AddrDccOut,
>> &AddrHtileIn, &AddrHtileOut);
>> if (r)
>> return r;
>> @@ -820,7 +822,7 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib,
>>
>> for (level = 0; level < config->info.levels; level++) {
>> r = gfx6_compute_level(addrlib, config, surf,
>> true, level, compressed,
>> - &AddrSurfInfoIn,
>> &AddrSurfInfoOut,
>> + shareable, &AddrSurfInfoIn,
>> &AddrSurfInfoOut,
>> &AddrDccIn, &AddrDccOut,
>> NULL, NULL);
>> if (r)
>> --
>> 2.17.0
>>
>> _______________________________________________
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>> mesa-dev at lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/mesa-dev
>
>
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