[Mesa-dev] [PATCH 3/9] intel/blorp: Rename blorp_ccs_resolve to blorp_ccs_op

[Jason Ekstrand]

We also make it capable of handling any aux op including fast-clear and
ambiguate.
---
 src/intel/blorp/blorp.h               | 10 ++++----
 src/intel/blorp/blorp_clear.c         | 46 ++++++++++++++++++++++++-----------
 src/intel/vulkan/anv_blorp.c          |  4 +--
 src/mesa/drivers/dri/i965/brw_blorp.c |  6 ++---
 4 files changed, 42 insertions(+), 24 deletions(-)

diff --git a/src/intel/blorp/blorp.h b/src/intel/blorp/blorp.h
index 4626f2f..8c775bf 100644
--- a/src/intel/blorp/blorp.h
+++ b/src/intel/blorp/blorp.h
@@ -201,11 +201,11 @@ blorp_clear_attachments(struct blorp_batch *batch,
                         uint8_t stencil_mask, uint8_t stencil_value);
 
 void
-blorp_ccs_resolve(struct blorp_batch *batch,
-                  struct blorp_surf *surf, uint32_t level,
-                  uint32_t start_layer, uint32_t num_layers,
-                  enum isl_format format,
-                  enum isl_aux_op resolve_op);
+blorp_ccs_op(struct blorp_batch *batch,
+             struct blorp_surf *surf, uint32_t level,
+             uint32_t start_layer, uint32_t num_layers,
+             enum isl_format format,
+             enum isl_aux_op ccs_op);
 
 void
 blorp_ccs_ambiguate(struct blorp_batch *batch,
diff --git a/src/intel/blorp/blorp_clear.c b/src/intel/blorp/blorp_clear.c
index 2ae783d..cdf14d2 100644
--- a/src/intel/blorp/blorp_clear.c
+++ b/src/intel/blorp/blorp_clear.c
@@ -815,12 +815,30 @@ blorp_clear_attachments(struct blorp_batch *batch,
 }
 
 void
-blorp_ccs_resolve(struct blorp_batch *batch,
-                  struct blorp_surf *surf, uint32_t level,
-                  uint32_t start_layer, uint32_t num_layers,
-                  enum isl_format format,
-                  enum isl_aux_op resolve_op)
+blorp_ccs_op(struct blorp_batch *batch,
+             struct blorp_surf *surf, uint32_t level,
+             uint32_t start_layer, uint32_t num_layers,
+             enum isl_format format,
+             enum isl_aux_op ccs_op)
 {
+   if (ccs_op == ISL_AUX_OP_FAST_CLEAR) {
+      blorp_fast_clear(batch, surf, format, level, start_layer, num_layers,
+                       0, 0,
+                       minify(surf->surf->logical_level0_px.w, level),
+                       minify(surf->surf->logical_level0_px.h, level));
+      return;
+   } else if (ISL_DEV_GEN(batch->blorp->isl_dev) < 10 &&
+              ccs_op == ISL_AUX_OP_AMBIGUATE) {
+      /* Prior to Cannonlake, the ambiguate is not available as a hardware
+       * operation.  Instead, we have to fake it by carefully binding the CCS
+       * as a render target and clearing it to 0.  We leave that complicated
+       * mess to another function.
+       */
+      for (uint32_t a = 0; a < num_layers; a++)
+         blorp_ccs_ambiguate(batch, surf, level, start_layer + a);
+      return;
+   }
+
    struct blorp_params params;
 
    blorp_params_init(&params);
@@ -858,17 +876,17 @@ blorp_ccs_resolve(struct blorp_batch *batch,
    params.y1 = ALIGN(params.y1, y_scaledown) / y_scaledown;
 
    if (batch->blorp->isl_dev->info->gen >= 10) {
-      assert(resolve_op == ISL_AUX_OP_FULL_RESOLVE ||
-             resolve_op == ISL_AUX_OP_PARTIAL_RESOLVE ||
-             resolve_op == ISL_AUX_OP_AMBIGUATE);
+      assert(ccs_op == ISL_AUX_OP_FULL_RESOLVE ||
+             ccs_op == ISL_AUX_OP_PARTIAL_RESOLVE ||
+             ccs_op == ISL_AUX_OP_AMBIGUATE);
    } else if (batch->blorp->isl_dev->info->gen >= 9) {
-      assert(resolve_op == ISL_AUX_OP_FULL_RESOLVE ||
-             resolve_op == ISL_AUX_OP_PARTIAL_RESOLVE);
+      assert(ccs_op == ISL_AUX_OP_FULL_RESOLVE ||
+             ccs_op == ISL_AUX_OP_PARTIAL_RESOLVE);
    } else {
       /* Broadwell and earlier do not have a partial resolve */
-      assert(resolve_op == ISL_AUX_OP_FULL_RESOLVE);
+      assert(ccs_op == ISL_AUX_OP_FULL_RESOLVE);
    }
-   params.fast_clear_op = resolve_op;
+   params.fast_clear_op = ccs_op;
    params.num_layers = num_layers;
 
    /* Note: there is no need to initialize push constants because it doesn't
@@ -1021,8 +1039,8 @@ blorp_ccs_ambiguate(struct blorp_batch *batch,
 {
    if (ISL_DEV_GEN(batch->blorp->isl_dev) >= 10) {
       /* On gen10 and above, we have a hardware resolve op for this */
-      return blorp_ccs_resolve(batch, surf, level, layer, 1,
-                               surf->surf->format, ISL_AUX_OP_AMBIGUATE);
+      return blorp_ccs_op(batch, surf, level, layer, 1,
+                          surf->surf->format, ISL_AUX_OP_AMBIGUATE);
    }
 
    struct blorp_params params;
diff --git a/src/intel/vulkan/anv_blorp.c b/src/intel/vulkan/anv_blorp.c
index c4a3e4a..7c4a022 100644
--- a/src/intel/vulkan/anv_blorp.c
+++ b/src/intel/vulkan/anv_blorp.c
@@ -1760,8 +1760,8 @@ anv_image_ccs_op(struct anv_cmd_buffer *cmd_buffer,
       break;
    case ISL_AUX_OP_FULL_RESOLVE:
    case ISL_AUX_OP_PARTIAL_RESOLVE:
-      blorp_ccs_resolve(&batch, &surf, level, base_layer, layer_count,
-                        surf.surf->format, ccs_op);
+      blorp_ccs_op(&batch, &surf, level, base_layer, layer_count,
+                   surf.surf->format, ccs_op);
       break;
    case ISL_AUX_OP_AMBIGUATE:
       for (uint32_t a = 0; a < layer_count; a++) {
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c
index f538cd0..dab04f2 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -1488,9 +1488,9 @@ brw_blorp_resolve_color(struct brw_context *brw, struct intel_mipmap_tree *mt,
 
    struct blorp_batch batch;
    blorp_batch_init(&brw->blorp, &batch, brw, 0);
-   blorp_ccs_resolve(&batch, &surf, level, layer, 1,
-                     brw_blorp_to_isl_format(brw, format, true),
-                     resolve_op);
+   blorp_ccs_op(&batch, &surf, level, layer, 1,
+                brw_blorp_to_isl_format(brw, format, true),
+                resolve_op);
    blorp_batch_finish(&batch);
 
    /* See comment above */
-- 
2.5.0.400.gff86faf