[Mesa-dev] [PATCH 6/6] radeonsi: set DB_EQAA.MAX_ANCHOR_SAMPLES correctly

Marek Olšák maraeo at gmail.com
Thu May 17 01:47:27 UTC 2018


From: Marek Olšák <marek.olsak at amd.com>

---
 src/gallium/drivers/radeonsi/si_state.c | 16 ++++++++++++----
 1 file changed, 12 insertions(+), 4 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index f4e29f68b29..3a7e928df53 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -3333,21 +3333,21 @@ static void si_emit_msaa_config(struct si_context *sctx)
 		S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
 		S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
 		S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
 		S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
 		S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
 		S_028A4C_FORCE_EOV_REZ_ENABLE(1);
 	unsigned db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
 			   S_028804_INCOHERENT_EQAA_READS(1) |
 			   S_028804_INTERPOLATE_COMP_Z(1) |
 			   S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
-	unsigned coverage_samples, color_samples;
+	unsigned coverage_samples, color_samples, z_samples;
 
 	/* S: Coverage samples (up to 16x):
 	 * - Scan conversion samples (PA_SC_AA_CONFIG.MSAA_NUM_SAMPLES)
 	 * - CB FMASK samples (CB_COLORi_ATTRIB.NUM_SAMPLES)
 	 *
 	 * Z: Z/S samples (up to 8x, must be <= coverage samples and >= color samples):
 	 * - Value seen by DB (DB_Z_INFO.NUM_SAMPLES)
 	 * - Value seen by CB, must be correct even if Z/S is unbound (DB_EQAA.MAX_ANCHOR_SAMPLES)
 	 * # Missing samples are derived from Z planes if Z is compressed (up to 16x quality), or
 	 * # from the closest defined sample if Z is uncompressed (same quality as the number of
@@ -3379,24 +3379,31 @@ static void si_emit_msaa_config(struct si_context *sctx)
 	 *   EQAA  8s 8z 2f - might look the same as 8x MSAA with low-density geometry
 	 *   EQAA  8s 4z 4f - might look the same as 8x MSAA if Z is compressed
 	 *   EQAA  8s 4z 2f - might look the same as 8x MSAA with low-density geometry if Z is compressed
 	 *   EQAA  4s 4z 4f = 4x MSAA
 	 *   EQAA  4s 4z 2f - might look the same as 4x MSAA with low-density geometry
 	 *   EQAA  2s 2z 2f = 2x MSAA
 	 */
 	if (sctx->framebuffer.nr_samples > 1) {
 		coverage_samples = sctx->framebuffer.nr_samples;
 		color_samples = sctx->framebuffer.nr_color_samples;
+
+		if (sctx->framebuffer.state.zsbuf) {
+			z_samples = sctx->framebuffer.state.zsbuf->texture->nr_samples;
+			z_samples = MAX2(1, z_samples);
+		} else {
+			z_samples = coverage_samples;
+		}
 	} else if (sctx->smoothing_enabled) {
-		coverage_samples = color_samples = SI_NUM_SMOOTH_AA_SAMPLES;
+		coverage_samples = color_samples = z_samples = SI_NUM_SMOOTH_AA_SAMPLES;
 	} else {
-		coverage_samples = color_samples = 1;
+		coverage_samples = color_samples = z_samples = 1;
 	}
 
 	/* Required by OpenGL line rasterization.
 	 *
 	 * TODO: We should also enable perpendicular endcaps for AA lines,
 	 *       but that requires implementing line stippling in the pixel
 	 *       shader. SC can only do line stippling with axis-aligned
 	 *       endcaps.
 	 */
 	unsigned sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
@@ -3404,34 +3411,35 @@ static void si_emit_msaa_config(struct si_context *sctx)
 	if (coverage_samples > 1) {
 		/* distance from the pixel center, indexed by log2(nr_samples) */
 		static unsigned max_dist[] = {
 			0, /* unused */
 			4, /* 2x MSAA */
 			6, /* 4x MSAA */
 			7, /* 8x MSAA */
 			8, /* 16x MSAA */
 		};
 		unsigned log_samples = util_logbase2(coverage_samples);
+		unsigned log_z_samples = util_logbase2(z_samples);
 		unsigned ps_iter_samples = si_get_ps_iter_samples(sctx);
 		unsigned log_ps_iter_samples = util_logbase2(ps_iter_samples);
 
 		radeon_set_context_reg_seq(cs, R_028BDC_PA_SC_LINE_CNTL, 2);
 		radeon_emit(cs, sc_line_cntl |
 			    S_028BDC_EXPAND_LINE_WIDTH(1)); /* R_028BDC_PA_SC_LINE_CNTL */
 		radeon_emit(cs, S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
 			    S_028BE0_MAX_SAMPLE_DIST(max_dist[log_samples]) |
 			    S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples)); /* R_028BE0_PA_SC_AA_CONFIG */
 
 		if (sctx->framebuffer.nr_samples > 1) {
 			radeon_set_context_reg(cs, R_028804_DB_EQAA,
 					       db_eqaa |
-					       S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
+					       S_028804_MAX_ANCHOR_SAMPLES(log_z_samples) |
 					       S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
 					       S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
 					       S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples));
 			radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1,
 					       S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1) |
 					       sc_mode_cntl_1);
 		} else if (sctx->smoothing_enabled) {
 			radeon_set_context_reg(cs, R_028804_DB_EQAA,
 					       db_eqaa |
 					       S_028804_OVERRASTERIZATION_AMOUNT(log_samples));
-- 
2.17.0



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