[Mesa-dev] [PATCH 2/2] radv: add radv_emit_shader_pointer() helper

[Samuel Pitoiset]

For future work (support for 32-bit GPU pointers).

Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
---
 src/amd/vulkan/radv_cmd_buffer.c | 13 ++++++-------
 src/amd/vulkan/radv_device.c     | 17 +++++++++++------
 src/amd/vulkan/radv_private.h    |  3 +++
 3 files changed, 20 insertions(+), 13 deletions(-)

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 1ca687494a..a8359ac092 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -587,9 +587,9 @@ radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
 		return;
 	assert(loc->num_sgprs == 2);
 	assert(!loc->indirect);
-	radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 2);
-	radeon_emit(cmd_buffer->cs, va);
-	radeon_emit(cmd_buffer->cs, va >> 32);
+
+	radv_emit_shader_pointer(cmd_buffer->cs,
+				 base_reg + loc->sgpr_idx * 4, va);
 }
 
 static void
@@ -1442,10 +1442,9 @@ emit_stage_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
 
 	assert(!desc_set_loc->indirect);
 	assert(desc_set_loc->num_sgprs == 2);
-	radeon_set_sh_reg_seq(cmd_buffer->cs,
-			      base_reg + desc_set_loc->sgpr_idx * 4, 2);
-	radeon_emit(cmd_buffer->cs, va);
-	radeon_emit(cmd_buffer->cs, va >> 32);
+
+	radv_emit_shader_pointer(cmd_buffer->cs,
+				 base_reg + desc_set_loc->sgpr_idx * 4, va);
 }
 
 static void
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index fa07ec40f3..91ab729d86 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -1941,6 +1941,15 @@ radv_emit_compute_scratch(struct radv_queue *queue, struct radeon_winsys_cs *cs,
 			S_008F04_SWIZZLE_ENABLE(1));
 }
 
+void
+radv_emit_shader_pointer(struct radeon_winsys_cs *cs,
+			 uint32_t sh_offset, uint64_t va)
+{
+	radeon_set_sh_reg_seq(cs, sh_offset, 2);
+	radeon_emit(cs, va);
+	radeon_emit(cs, va >> 32);
+}
+
 static void
 radv_emit_global_shader_pointers(struct radv_queue *queue,
 				 struct radeon_winsys_cs *cs,
@@ -1962,9 +1971,7 @@ radv_emit_global_shader_pointers(struct radv_queue *queue,
 				   R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
 
 		for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
-			radeon_set_sh_reg_seq(cs, regs[i], 2);
-			radeon_emit(cs, va);
-			radeon_emit(cs, va >> 32);
+			radv_emit_shader_pointer(cs, regs[i], va);
 		}
 	} else {
 		uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
@@ -1975,9 +1982,7 @@ radv_emit_global_shader_pointers(struct radv_queue *queue,
 				   R_00B530_SPI_SHADER_USER_DATA_LS_0};
 
 		for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
-			radeon_set_sh_reg_seq(cs, regs[i], 2);
-			radeon_emit(cs, va);
-			radeon_emit(cs, va >> 32);
+			radv_emit_shader_pointer(cs, regs[i], va);
 		}
 	}
 }
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index 304ed17f01..05733c7eb9 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -1128,6 +1128,9 @@ bool radv_get_memory_fd(struct radv_device *device,
 			struct radv_device_memory *memory,
 			int *pFD);
 
+void radv_emit_shader_pointer(struct radeon_winsys_cs *cs,
+			      uint32_t sh_offset, uint64_t va);
+
 static inline struct radv_descriptor_state *
 radv_get_descriptors_state(struct radv_cmd_buffer *cmd_buffer,
 			   VkPipelineBindPoint bind_point)
-- 
2.17.0