[Mesa-dev] [PATCH 52/53] intel/fs: Support SIMD32 repclear shaders

[Jason Ekstrand]

---
 src/intel/compiler/brw_fs.cpp           | 83 ++++++++++++++++++++++-----------
 src/intel/compiler/brw_fs_generator.cpp |  2 +-
 2 files changed, 57 insertions(+), 28 deletions(-)

diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index 7e532af..c821a11 100644
--- a/src/intel/compiler/brw_fs.cpp
+++ b/src/intel/compiler/brw_fs.cpp
@@ -3218,49 +3218,78 @@ void
 fs_visitor::emit_repclear_shader()
 {
    brw_wm_prog_key *key = (brw_wm_prog_key*) this->key;
-   int base_mrf = 0;
-   int color_mrf = base_mrf + 2;
+
+   assert(dispatch_width >= 16);
+
+   /* The payload moves between SIMD16 and SIMD32 */
+   unsigned payload_start_grf = dispatch_width == 16 ? 2 : 3;
 
    const struct brw_reg color_in_reg =
-      brw_reg(BRW_GENERAL_REGISTER_FILE, 2, 3, 0, 0, BRW_REGISTER_TYPE_F,
+      brw_reg(BRW_GENERAL_REGISTER_FILE, payload_start_grf, 3,
+              0, 0, BRW_REGISTER_TYPE_F,
               BRW_VERTICAL_STRIDE_8, BRW_WIDTH_2, BRW_HORIZONTAL_STRIDE_4,
               BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
 
-   bld.exec_all().group(4, 0)
-      .MOV(vec4(brw_message_reg(color_mrf)), fs_reg(color_in_reg));
-
    fs_inst *write = NULL;
    if (key->nr_color_regions == 1) {
-      write = bld.emit(FS_OPCODE_REP_FB_WRITE);
-      write->saturate = key->clamp_fragment_color;
-      write->base_mrf = color_mrf;
-      write->target = 0;
-      write->header_size = 0;
-      write->mlen = 1;
+      const int base_mrf = 0;
+      bld.exec_all().group(4, 0)
+         .MOV(vec4(brw_message_reg(base_mrf)), fs_reg(color_in_reg));
+
+      for (unsigned g = 0; g < dispatch_width / 16; g++) {
+         write = bld.group(16, g).emit(FS_OPCODE_REP_FB_WRITE);
+         write->saturate = key->clamp_fragment_color;
+         write->base_mrf = base_mrf;
+         write->target = 0;
+         write->header_size = 0;
+         write->mlen = 1;
+         write->last_rt = true;
+      }
    } else {
       assume(key->nr_color_regions > 0);
 
-      struct brw_reg header =
-         retype(brw_message_reg(base_mrf), BRW_REGISTER_TYPE_UD);
+      /* For MRT, we need separate messages for the high and low render target
+       * writes because they have different headers.
+       */
+      const int base_mrf[2] = { 0, 4 };
+
       bld.exec_all().group(16, 0)
-         .MOV(header, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
+         .MOV(retype(brw_message_reg(base_mrf[0]), BRW_REGISTER_TYPE_UD),
+              retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
+      bld.exec_all().group(4, 0)
+         .MOV(vec4(brw_message_reg(base_mrf[0] + 2)), fs_reg(color_in_reg));
+
+      if (dispatch_width > 16) {
+         bld.exec_all().group(8, 0)
+            .MOV(retype(brw_message_reg(base_mrf[1] + 0), BRW_REGISTER_TYPE_UD),
+                 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
+         bld.exec_all().group(8, 0)
+            .MOV(retype(brw_message_reg(base_mrf[1] + 1), BRW_REGISTER_TYPE_UD),
+                 retype(brw_vec8_grf(2, 0), BRW_REGISTER_TYPE_UD));
+         bld.exec_all().group(4, 0)
+            .MOV(vec4(brw_message_reg(base_mrf[1] + 2)), fs_reg(color_in_reg));
+      }
 
       for (int i = 0; i < key->nr_color_regions; ++i) {
-         if (i > 0) {
-            bld.exec_all().group(1, 0)
-               .MOV(component(header, 2), brw_imm_ud(i));
-         }
+         for (unsigned g = 0; g < dispatch_width / 16; g++) {
+            if (i > 0) {
+               const fs_reg header =
+                  retype(brw_message_reg(base_mrf[g]), BRW_REGISTER_TYPE_UD);
+               bld.exec_all().group(1, 0)
+                  .MOV(component(header, 2), brw_imm_ud(i));
+            }
 
-         write = bld.emit(FS_OPCODE_REP_FB_WRITE);
-         write->saturate = key->clamp_fragment_color;
-         write->base_mrf = base_mrf;
-         write->target = i;
-         write->header_size = 2;
-         write->mlen = 3;
+            write = bld.group(16, g).emit(FS_OPCODE_REP_FB_WRITE);
+            write->saturate = key->clamp_fragment_color;
+            write->base_mrf = base_mrf[g];
+            write->target = i;
+            write->header_size = 2;
+            write->mlen = 3;
+            write->last_rt = (i == key->nr_color_regions - 1);
+         }
       }
    }
    write->eot = true;
-   write->last_rt = true;
 
    calculate_cfg();
 
@@ -6728,7 +6757,7 @@ fs_visitor::run_fs(bool allow_spilling, bool do_rep_send)
    if (0) {
       emit_dummy_fs();
    } else if (do_rep_send) {
-      assert(dispatch_width == 16);
+      assert(dispatch_width >= 16);
       emit_repclear_shader();
    } else {
       if (shader_time_index >= 0)
diff --git a/src/intel/compiler/brw_fs_generator.cpp b/src/intel/compiler/brw_fs_generator.cpp
index f0de9ce..493936b 100644
--- a/src/intel/compiler/brw_fs_generator.cpp
+++ b/src/intel/compiler/brw_fs_generator.cpp
@@ -272,7 +272,7 @@ fs_generator::fire_fb_write(fs_inst *inst,
    }
 
    if (inst->opcode == FS_OPCODE_REP_FB_WRITE) {
-      assert(inst->group == 0 && inst->exec_size == 16);
+      assert(inst->exec_size == 16);
       msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED;
 
    } else if (prog_data->dual_src_blend) {
-- 
2.5.0.400.gff86faf