[Mesa-dev] [PATCH 41/53] intel/fs: Fix Gen7 compressed source region alignment restriction for SIMD32

[Jason Ekstrand]

On Thu, May 31, 2018 at 10:31 AM, Matt Turner <mattst88 at gmail.com> wrote:

> On Thu, May 24, 2018 at 2:56 PM, Jason Ekstrand <jason at jlekstrand.net>
> wrote:
> > From: Francisco Jerez <currojerez at riseup.net>
> >
> > Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
> > ---
> >  src/intel/compiler/brw_fs.cpp | 8 +++++++-
> >  1 file changed, 7 insertions(+), 1 deletion(-)
> >
> > diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.
> cpp
> > index f583900..ae59716 100644
> > --- a/src/intel/compiler/brw_fs.cpp
> > +++ b/src/intel/compiler/brw_fs.cpp
> > @@ -5088,8 +5088,14 @@ get_fpu_lowered_simd_width(const struct
> gen_device_info *devinfo,
> >              type_sz(inst->dst.type) == 4 && inst->dst.stride == 1 &&
> >              type_sz(inst->src[i].type) == 2 && inst->src[i].stride == 1;
> >
> > +         /* We check size_read(i) against size_written instead of
> REG_SIZE
> > +          * because we want to properly handle SIMD32.  In SIMD32, you
> can end
> > +          * up which writes 4 registers and a source that reads 2
> registers
>
> This reads a little strangely. Maybe "you can end up with writes to 4
> registers and a source that reads 2 registers"
>

Yeah, I think that's better.  I wouldn't say it's now "good" but it is
better.
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