[Mesa-dev] [PATCH 00/11] intel/fs: Add a generic SEND opcode and use it on

[Eero Tamminen]

Hi,

On 3.11.2018 2.06, Jason Ekstrand wrote:
> This patch series is something we've talked about doing for a while and
> haven't gotten around to yet.  It implements a generic SEND opcode and then
> reworks a bunch of the current SEND instructions such as texturing to use
> that instead of piles of shader codegen.  Among other things, this gives us
> substantially better scheduling of instructions around indirect sends.
> They currently generate up to 5 ALU instructions in the generator to build
> the indirect descriptor and this is reduced to 1 with the other 4 happening
> in the IR level where we can schedule.

Would that have any impact on (currently missing) GEN9+ SENDS support?

Splitted send message uses 2 register ranges which can be independently
allocated & updated (can improve performance in cases like MRT and blur
shaders with several consecutive & partly similar sends).

I.e. instructions updating those register ranges should be scheduled
differently to get advantage of SENDS.  Would that need to be taken
into account at IR level too?


	- Eero

> Jason Ekstrand (11):
>    intel/defines: Explicitly cast to uint32_t in SET_FIELD and SET_BITS
>    intel/fs: Handle IMAGE_SIZE in size_read() and is_send_from_grf()
>    intel/fs: Take an explicit exec size in brw_surface_payload_size()
>    intel/eu: Add has_simd4x2 bools to surface_write functions
>    intel/eu: Rework surface descriptor helpers
>    intel/fs: Add a generic SEND opcode
>    intel/fs: Use the generic SEND opcode for surface messages
>    intel/fs: Mark texture surfaces used in brw_fs_nir
>    intel/fs: Use a logical opcode for IMAGE_SIZE
>    intel/fs: Use SHADER_OPCODE_SEND for texturing on gen7+
>    intel/fs: Use SHADER_OPCODE_SEND for varying UBO pulls on gen7+
> 
>   src/intel/compiler/brw_eu.h                   | 237 +++++++++--
>   src/intel/compiler/brw_eu_defines.h           |  13 +-
>   src/intel/compiler/brw_eu_emit.c              | 376 +++---------------
>   src/intel/compiler/brw_fs.cpp                 | 371 ++++++++++++++---
>   src/intel/compiler/brw_fs.h                   |  12 +-
>   src/intel/compiler/brw_fs_cse.cpp             |   6 +-
>   src/intel/compiler/brw_fs_generator.cpp       | 334 +++-------------
>   src/intel/compiler/brw_fs_nir.cpp             |  30 +-
>   src/intel/compiler/brw_fs_reg_allocate.cpp    |   6 +-
>   .../compiler/brw_schedule_instructions.cpp    |  90 ++++-
>   src/intel/compiler/brw_shader.cpp             |  10 +-
>   src/intel/compiler/brw_shader.h               |   5 +
>   src/mesa/drivers/dri/i965/brw_defines.h       |   2 +-
>   13 files changed, 778 insertions(+), 714 deletions(-)
>