[Mesa-dev] [PATCH v2] radv: set optimal OVERWRITE_COMBINER_WATERMARK on GFX9

[Bas Nieuwenhuizen]

Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
On Mon, Nov 12, 2018 at 9:44 AM Samuel Pitoiset
<samuel.pitoiset at gmail.com> wrote:
>
> Ported from RadeonSI.
>
> v2: - use the current subpass instead of the whole fb
>
> Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
> ---
>  src/amd/vulkan/radv_cmd_buffer.c | 21 +++++++++++++++++++++
>  src/amd/vulkan/si_cmd_buffer.c   |  3 ---
>  2 files changed, 21 insertions(+), 3 deletions(-)
>
> diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
> index ee5373950f..950dbb00a9 100644
> --- a/src/amd/vulkan/radv_cmd_buffer.c
> +++ b/src/amd/vulkan/radv_cmd_buffer.c
> @@ -1483,6 +1483,7 @@ radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
>         int i;
>         struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
>         const struct radv_subpass *subpass = cmd_buffer->state.subpass;
> +       unsigned num_bpp64_colorbufs = 0;
>
>         /* this may happen for inherited secondary recording */
>         if (!framebuffer)
> @@ -1506,6 +1507,9 @@ radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
>                 radv_emit_fb_color_state(cmd_buffer, i, att, image, layout);
>
>                 radv_load_color_clear_metadata(cmd_buffer, image, i);
> +
> +               if (image->surface.bpe >= 8)
> +                       num_bpp64_colorbufs++;
>         }
>
>         if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
> @@ -1541,6 +1545,23 @@ radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
>                                S_028208_BR_X(framebuffer->width) |
>                                S_028208_BR_Y(framebuffer->height));
>
> +       if (cmd_buffer->device->physical_device->rad_info.chip_class >= VI) {
> +               uint8_t watermark = 4; /* Default value for VI. */
> +
> +               /* For optimal DCC performance. */
> +               if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
> +                       if (num_bpp64_colorbufs >= 5) {
> +                               watermark = 8;
> +                       } else {
> +                               watermark = 6;
> +                       }
> +               }
> +
> +               radeon_set_context_reg(cmd_buffer->cs, R_028424_CB_DCC_CONTROL,
> +                                      S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
> +                                      S_028424_OVERWRITE_COMBINER_WATERMARK(watermark));
> +       }
> +
>         if (cmd_buffer->device->dfsm_allowed) {
>                 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
>                 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
> diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c
> index f4da2b38fd..a9f2572541 100644
> --- a/src/amd/vulkan/si_cmd_buffer.c
> +++ b/src/amd/vulkan/si_cmd_buffer.c
> @@ -305,9 +305,6 @@ si_emit_graphics(struct radv_physical_device *physical_device,
>
>         if (physical_device->rad_info.chip_class >= VI) {
>                 uint32_t vgt_tess_distribution;
> -               radeon_set_context_reg(cs, R_028424_CB_DCC_CONTROL,
> -                                      S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
> -                                      S_028424_OVERWRITE_COMBINER_WATERMARK(4));
>
>                 vgt_tess_distribution = S_028B50_ACCUM_ISOLINE(32) |
>                         S_028B50_ACCUM_TRI(11) |
> --
> 2.19.1
>
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