[Mesa-dev] [PATCH v2] radv: remove dependency on addrlib gfx9_enum.h

Nicolai Hähnle nhaehnle at gmail.com
Mon Nov 19 21:28:21 UTC 2018


From: Nicolai Hähnle <nicolai.haehnle at amd.com>

v2:
- use SI_CONTEXT_REG_OFFSET

Reviewed-by: Dave Airlie <airlied at redhat.com>
---
 src/amd/common/sid.h             | 3 +++
 src/amd/vulkan/radv_cmd_buffer.c | 6 ++----
 src/amd/vulkan/radv_device.c     | 9 ++++-----
 3 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/src/amd/common/sid.h b/src/amd/common/sid.h
index 35782046dd5..49683f1aa5a 100644
--- a/src/amd/common/sid.h
+++ b/src/amd/common/sid.h
@@ -2429,20 +2429,23 @@
 #define   C_008F30_ANISO_BIAS                                         0xF81FFFFF
 #define   S_008F30_TRUNC_COORD(x)                                     (((unsigned)(x) & 0x1) << 27)
 #define   G_008F30_TRUNC_COORD(x)                                     (((x) >> 27) & 0x1)
 #define   C_008F30_TRUNC_COORD                                        0xF7FFFFFF
 #define   S_008F30_DISABLE_CUBE_WRAP(x)                               (((unsigned)(x) & 0x1) << 28)
 #define   G_008F30_DISABLE_CUBE_WRAP(x)                               (((x) >> 28) & 0x1)
 #define   C_008F30_DISABLE_CUBE_WRAP                                  0xEFFFFFFF
 #define   S_008F30_FILTER_MODE(x)                                     (((unsigned)(x) & 0x03) << 29)
 #define   G_008F30_FILTER_MODE(x)                                     (((x) >> 29) & 0x03)
 #define   C_008F30_FILTER_MODE                                        0x9FFFFFFF
+#define     V_008F30_SQ_IMG_FILTER_MODE_BLEND                       0x00
+#define     V_008F30_SQ_IMG_FILTER_MODE_MIN                         0x01
+#define     V_008F30_SQ_IMG_FILTER_MODE_MAX                         0x02
 /* VI */
 #define   S_008F30_COMPAT_MODE(x)                                     (((unsigned)(x) & 0x1) << 31)
 #define   G_008F30_COMPAT_MODE(x)                                     (((x) >> 31) & 0x1)
 #define   C_008F30_COMPAT_MODE                                        0x7FFFFFFF
 /*    */
 #define R_008F34_SQ_IMG_SAMP_WORD1                                      0x008F34
 #define   S_008F34_MIN_LOD(x)                                         (((unsigned)(x) & 0xFFF) << 0)
 #define   G_008F34_MIN_LOD(x)                                         (((x) >> 0) & 0xFFF)
 #define   C_008F34_MIN_LOD                                            0xFFFFF000
 #define   S_008F34_MAX_LOD(x)                                         (((unsigned)(x) & 0xFFF) << 12)
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 8e0ed284d65..efec0424349 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -30,22 +30,20 @@
 #include "radv_shader.h"
 #include "radv_cs.h"
 #include "sid.h"
 #include "gfx9d.h"
 #include "vk_format.h"
 #include "radv_debug.h"
 #include "radv_meta.h"
 
 #include "ac_debug.h"
 
-#include "addrlib/gfx9/chip/gfx9_enum.h"
-
 enum {
 	RADV_PREFETCH_VBO_DESCRIPTORS	= (1 << 0),
 	RADV_PREFETCH_VS		= (1 << 1),
 	RADV_PREFETCH_TCS		= (1 << 2),
 	RADV_PREFETCH_TES		= (1 << 3),
 	RADV_PREFETCH_GS		= (1 << 4),
 	RADV_PREFETCH_PS		= (1 << 5),
 	RADV_PREFETCH_SHADERS		= (RADV_PREFETCH_VS  |
 					   RADV_PREFETCH_TCS |
 					   RADV_PREFETCH_TES |
@@ -1314,21 +1312,21 @@ radv_load_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
 	}
 	if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
 		++reg_count;
 
 	uint32_t reg = R_028028_DB_STENCIL_CLEAR + 4 * reg_offset;
 
 	if (cmd_buffer->device->physical_device->rad_info.chip_class >= VI) {
 		radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, 0));
 		radeon_emit(cs, va);
 		radeon_emit(cs, va >> 32);
-		radeon_emit(cs, (reg >> 2) - CONTEXT_SPACE_START);
+		radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
 		radeon_emit(cs, reg_count);
 	} else {
 		radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
 		radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
 				COPY_DATA_DST_SEL(COPY_DATA_REG) |
 				(reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
 		radeon_emit(cs, va);
 		radeon_emit(cs, va >> 32);
 		radeon_emit(cs, reg >> 2);
 		radeon_emit(cs, 0);
@@ -1452,21 +1450,21 @@ radv_load_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
 
 	if (!radv_image_has_cmask(image) && !radv_image_has_dcc(image))
 		return;
 
 	uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c;
 
 	if (cmd_buffer->device->physical_device->rad_info.chip_class >= VI) {
 		radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, cmd_buffer->state.predicating));
 		radeon_emit(cs, va);
 		radeon_emit(cs, va >> 32);
-		radeon_emit(cs, (reg >> 2) - CONTEXT_SPACE_START);
+		radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
 		radeon_emit(cs, 2);
 	} else {
 		/* TODO: Figure out how to use LOAD_CONTEXT_REG on SI/CIK. */
 		radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
 		radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
 				COPY_DATA_DST_SEL(COPY_DATA_REG) |
 				COPY_DATA_COUNT_SEL);
 		radeon_emit(cs, va);
 		radeon_emit(cs, va >> 32);
 		radeon_emit(cs, reg >> 2);
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 70084a2b605..ad057a87509 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -38,21 +38,20 @@
 #include "vk_util.h"
 #include <xf86drm.h>
 #include <amdgpu.h>
 #include <amdgpu_drm.h>
 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
 #include "ac_llvm_util.h"
 #include "vk_format.h"
 #include "sid.h"
 #include "git_sha1.h"
 #include "gfx9d.h"
-#include "addrlib/gfx9/chip/gfx9_enum.h"
 #include "util/build_id.h"
 #include "util/debug.h"
 #include "util/mesa-sha1.h"
 
 static int
 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
 {
 	struct mesa_sha1 ctx;
 	unsigned char sha1[20];
 	unsigned ptr_size = sizeof(void*);
@@ -4519,25 +4518,25 @@ radv_tex_aniso_filter(unsigned filter)
 	if (filter < 16)
 		return 3;
 	return 4;
 }
 
 static unsigned
 radv_tex_filter_mode(VkSamplerReductionModeEXT mode)
 {
 	switch (mode) {
 	case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT:
-		return SQ_IMG_FILTER_MODE_BLEND;
+		return V_008F30_SQ_IMG_FILTER_MODE_BLEND;
 	case VK_SAMPLER_REDUCTION_MODE_MIN_EXT:
-		return SQ_IMG_FILTER_MODE_MIN;
+		return V_008F30_SQ_IMG_FILTER_MODE_MIN;
 	case VK_SAMPLER_REDUCTION_MODE_MAX_EXT:
-		return SQ_IMG_FILTER_MODE_MAX;
+		return V_008F30_SQ_IMG_FILTER_MODE_MAX;
 	default:
 		break;
 	}
 	return 0;
 }
 
 static uint32_t
 radv_get_max_anisotropy(struct radv_device *device,
 			const VkSamplerCreateInfo *pCreateInfo)
 {
@@ -4552,21 +4551,21 @@ radv_get_max_anisotropy(struct radv_device *device,
 }
 
 static void
 radv_init_sampler(struct radv_device *device,
 		  struct radv_sampler *sampler,
 		  const VkSamplerCreateInfo *pCreateInfo)
 {
 	uint32_t max_aniso = radv_get_max_anisotropy(device, pCreateInfo);
 	uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
 	bool is_vi = (device->physical_device->rad_info.chip_class >= VI);
-	unsigned filter_mode = SQ_IMG_FILTER_MODE_BLEND;
+	unsigned filter_mode = V_008F30_SQ_IMG_FILTER_MODE_BLEND;
 
 	const struct VkSamplerReductionModeCreateInfoEXT *sampler_reduction =
 		vk_find_struct_const(pCreateInfo->pNext,
 				     SAMPLER_REDUCTION_MODE_CREATE_INFO_EXT);
 	if (sampler_reduction)
 		filter_mode = radv_tex_filter_mode(sampler_reduction->reductionMode);
 
 	sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
 			     S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
 			     S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
-- 
2.19.1



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