[Mesa-dev] [PATCH 1/3] radv: implement some SW counters
Samuel Pitoiset
samuel.pitoiset at gmail.com
Thu Nov 22 18:11:29 UTC 2018
Oops.
I was not planning to send this one. Please ignore.
On 11/22/18 7:10 PM, Samuel Pitoiset wrote:
> Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
> ---
> src/amd/vulkan/radv_cmd_buffer.c | 23 +++++++
> src/amd/vulkan/radv_device.c | 4 ++
> src/amd/vulkan/radv_meta.c | 2 +
> src/amd/vulkan/radv_meta_buffer.c | 6 ++
> src/amd/vulkan/radv_meta_clear.c | 11 ++++
> src/amd/vulkan/radv_meta_copy.c | 6 ++
> src/amd/vulkan/radv_meta_decompress.c | 1 +
> src/amd/vulkan/radv_meta_fast_clear.c | 3 +
> src/amd/vulkan/radv_meta_resolve.c | 2 +
> src/amd/vulkan/radv_meta_resolve_cs.c | 1 +
> src/amd/vulkan/radv_meta_resolve_fs.c | 2 +
> src/amd/vulkan/radv_private.h | 51 ++++++++++++++++
> src/amd/vulkan/radv_wsi.c | 87 +++++++++++++++++++++++++++
> src/amd/vulkan/si_cmd_buffer.c | 19 ++++++
> 14 files changed, 218 insertions(+)
>
> diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
> index f13768b4ada..7367e24fd28 100644
> --- a/src/amd/vulkan/radv_cmd_buffer.c
> +++ b/src/amd/vulkan/radv_cmd_buffer.c
> @@ -907,6 +907,8 @@ radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
> cmd_buffer->state.emitted_pipeline = pipeline;
>
> cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
> +
> + cmd_buffer->counters.counters[RADV_NUM_EMITTED_PIPELINES]++;
> }
>
> static void
> @@ -1822,6 +1824,10 @@ radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
>
> if (unlikely(cmd_buffer->device->trace_bo))
> radv_save_descriptors(cmd_buffer, bind_point);
> +
> + assert(cmd_buffer->cs->cdw <= cdw_max);
> +
> + cmd_buffer->counters.counters[RADV_NUM_FLUSH_DESCRIPTORS]++;
> }
>
> static void
> @@ -1878,6 +1884,8 @@ radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
>
> cmd_buffer->push_constant_stages &= ~stages;
> assert(cmd_buffer->cs->cdw <= cdw_max);
> +
> + cmd_buffer->counters.counters[RADV_NUM_FLUSH_CONSTANTS]++;
> }
>
> static void
> @@ -1929,6 +1937,8 @@ radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer,
> cmd_buffer->state.vb_va = va;
> cmd_buffer->state.vb_size = count * 16;
> cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_VBO_DESCRIPTORS;
> +
> + cmd_buffer->counters.counters[RADV_NUM_VB_UPDATES]++;
> }
> cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
> }
> @@ -2463,6 +2473,7 @@ VkResult radv_BeginCommandBuffer(
> }
>
> memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
> + memset(&cmd_buffer->counters, 0, sizeof(cmd_buffer->counters));
> cmd_buffer->state.last_primitive_reset_en = -1;
> cmd_buffer->state.last_index_type = -1;
> cmd_buffer->state.last_num_instances = -1;
> @@ -2816,6 +2827,8 @@ radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
>
> if (unlikely(cmd_buffer->device->trace_bo))
> radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
> +
> + cmd_buffer->counters.counters[RADV_NUM_EMITTED_PIPELINES]++;
> }
>
> static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer,
> @@ -3710,6 +3723,8 @@ radv_draw(struct radv_cmd_buffer *cmd_buffer,
>
> assert(cmd_buffer->cs->cdw <= cdw_max);
> radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_PS_PARTIAL_FLUSH);
> +
> + cmd_buffer->counters.counters[RADV_NUM_DRAW_CALLS]++;
> }
>
> void radv_CmdDraw(
> @@ -4105,6 +4120,8 @@ radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
> }
>
> radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);
> +
> + cmd_buffer->counters.counters[RADV_NUM_DISPATCH_CALLS]++;
> }
>
> void radv_CmdDispatchBase(
> @@ -4233,6 +4250,8 @@ static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
> aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
>
> radv_set_ds_clear_metadata(cmd_buffer, image, value, aspects);
> +
> + cmd_buffer->counters.counters[RADV_NUM_HTILE_INITS]++;
> }
>
> static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
> @@ -4283,6 +4302,8 @@ static void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
> state->flush_bits |= radv_clear_cmask(cmd_buffer, image, value);
>
> state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
> +
> + cmd_buffer->counters.counters[RADV_NUM_CMASK_INITS]++;
> }
>
> void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
> @@ -4297,6 +4318,8 @@ void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
>
> state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
> RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
> +
> + cmd_buffer->counters.counters[RADV_NUM_DCC_INITS]++;
> }
>
> /**
> diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
> index 70084a2b605..91f8db6f3bc 100644
> --- a/src/amd/vulkan/radv_device.c
> +++ b/src/amd/vulkan/radv_device.c
> @@ -2772,6 +2772,10 @@ VkResult radv_QueueSubmit(
> can_patch = false;
>
> cmd_buffer->status = RADV_CMD_BUFFER_STATUS_PENDING;
> +
> + for(unsigned k = 0; k < RADV_NUM_COUNTERS; k++) {
> + queue->device->counters.counters[k] += cmd_buffer->counters.counters[k];
> + }
> }
>
> for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += advance) {
> diff --git a/src/amd/vulkan/radv_meta.c b/src/amd/vulkan/radv_meta.c
> index 1ec8896afa2..8f03b3941a1 100644
> --- a/src/amd/vulkan/radv_meta.c
> +++ b/src/amd/vulkan/radv_meta.c
> @@ -97,6 +97,8 @@ radv_meta_save(struct radv_meta_saved_state *state,
> state->attachments = cmd_buffer->state.attachments;
> state->render_area = cmd_buffer->state.render_area;
> }
> +
> + cmd_buffer->counters.counters[RADV_NUM_META_OPERATIONS]++;
> }
>
> void
> diff --git a/src/amd/vulkan/radv_meta_buffer.c b/src/amd/vulkan/radv_meta_buffer.c
> index 76854d7bbad..a79232d7168 100644
> --- a/src/amd/vulkan/radv_meta_buffer.c
> +++ b/src/amd/vulkan/radv_meta_buffer.c
> @@ -329,6 +329,8 @@ static void fill_buffer_shader(struct radv_cmd_buffer *cmd_buffer,
> radv_CmdDispatch(radv_cmd_buffer_to_handle(cmd_buffer), block_count, 1, 1);
>
> radv_meta_restore(&saved_state, cmd_buffer);
> +
> + cmd_buffer->counters.counters[RADV_NUM_CS_CLEARS]++;
> }
>
> static void copy_buffer_shader(struct radv_cmd_buffer *cmd_buffer,
> @@ -395,6 +397,8 @@ static void copy_buffer_shader(struct radv_cmd_buffer *cmd_buffer,
> radv_CmdDispatch(radv_cmd_buffer_to_handle(cmd_buffer), block_count, 1, 1);
>
> radv_meta_restore(&saved_state, cmd_buffer);
> +
> + cmd_buffer->counters.counters[RADV_NUM_CS_COPIES]++;
> }
>
>
> @@ -537,4 +541,6 @@ void radv_CmdUpdateBuffer(
> radv_copy_buffer(cmd_buffer, cmd_buffer->upload.upload_bo, dst_buffer->bo,
> buf_offset, dstOffset + dst_buffer->offset, dataSize);
> }
> +
> + cmd_buffer->counters.counters[RADV_NUM_UPDATE_BUFFERS]++;
> }
> diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c
> index bf88d3a84d9..e82b6fd2f58 100644
> --- a/src/amd/vulkan/radv_meta_clear.c
> +++ b/src/amd/vulkan/radv_meta_clear.c
> @@ -451,6 +451,8 @@ emit_color_clear(struct radv_cmd_buffer *cmd_buffer,
> }
>
> radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
> +
> + cmd_buffer->counters.counters[RADV_NUM_SLOW_COLOR_CLEARS]++;
> }
>
>
> @@ -656,6 +658,10 @@ pick_depthstencil_pipeline(struct radv_cmd_buffer *cmd_buffer,
> /* we don't know the previous clear values, so we always have
> * the NO_EXPCLEAR path */
> index = DEPTH_CLEAR_FAST_NO_EXPCLEAR;
> +
> + cmd_buffer->counters.counters[RADV_NUM_FAST_DEPTH_CLEARS]++;
> + } else {
> + cmd_buffer->counters.counters[RADV_NUM_SLOW_DEPTH_CLEARS]++;
> }
>
> switch (aspects) {
> @@ -971,6 +977,8 @@ emit_fast_htile_clear(struct radv_cmd_buffer *cmd_buffer,
> *post_flush |= flush_bits;
> }
>
> + cmd_buffer->counters.counters[RADV_NUM_FAST_DEPTH_CLEARS]++;
> +
> return true;
> }
>
> @@ -1456,6 +1464,7 @@ emit_fast_color_clear(struct radv_cmd_buffer *cmd_buffer,
> radv_update_color_clear_metadata(cmd_buffer, iview->image, subpass_att,
> clear_color);
>
> + cmd_buffer->counters.counters[RADV_NUM_FAST_COLOR_CLEARS]++;
> return true;
> }
>
> @@ -1862,4 +1871,6 @@ void radv_CmdClearAttachments(
>
> radv_meta_restore(&saved_state, cmd_buffer);
> cmd_buffer->state.flush_bits |= post_flush;
> +
> + cmd_buffer->counters.counters[RADV_NUM_CLEAR_ATTACHMENTS]++;
> }
> diff --git a/src/amd/vulkan/radv_meta_copy.c b/src/amd/vulkan/radv_meta_copy.c
> index ddfb5c54673..1fd12850bf8 100644
> --- a/src/amd/vulkan/radv_meta_copy.c
> +++ b/src/amd/vulkan/radv_meta_copy.c
> @@ -223,6 +223,8 @@ meta_copy_buffer_to_image(struct radv_cmd_buffer *cmd_buffer,
> cmd_buffer->state.predicating = old_predicating;
>
> radv_meta_restore(&saved_state, cmd_buffer);
> +
> + cmd_buffer->counters.counters[RADV_NUM_B2I_COPIES]++;
> }
>
> void radv_CmdCopyBufferToImage(
> @@ -338,6 +340,8 @@ meta_copy_image_to_buffer(struct radv_cmd_buffer *cmd_buffer,
> cmd_buffer->state.predicating = old_predicating;
>
> radv_meta_restore(&saved_state, cmd_buffer);
> +
> + cmd_buffer->counters.counters[RADV_NUM_I2B_COPIES]++;
> }
>
> void radv_CmdCopyImageToBuffer(
> @@ -504,6 +508,8 @@ meta_copy_image(struct radv_cmd_buffer *cmd_buffer,
> cmd_buffer->state.predicating = old_predicating;
>
> radv_meta_restore(&saved_state, cmd_buffer);
> +
> + cmd_buffer->counters.counters[RADV_NUM_IMAGE_COPIES]++;
> }
>
> void radv_CmdCopyImage(
> diff --git a/src/amd/vulkan/radv_meta_decompress.c b/src/amd/vulkan/radv_meta_decompress.c
> index b4f568ba2f8..0bb77ce0583 100644
> --- a/src/amd/vulkan/radv_meta_decompress.c
> +++ b/src/amd/vulkan/radv_meta_decompress.c
> @@ -457,6 +457,7 @@ void radv_decompress_depth_image_inplace(struct radv_cmd_buffer *cmd_buffer,
> {
> assert(cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL);
> radv_process_depth_image_inplace(cmd_buffer, image, subresourceRange, DEPTH_DECOMPRESS);
> + cmd_buffer->counters.counters[RADV_NUM_HTILE_DECOMPRESSIONS]++;
> }
>
> void radv_resummarize_depth_image_inplace(struct radv_cmd_buffer *cmd_buffer,
> diff --git a/src/amd/vulkan/radv_meta_fast_clear.c b/src/amd/vulkan/radv_meta_fast_clear.c
> index a54b78c2a6c..3f5d0054046 100644
> --- a/src/amd/vulkan/radv_meta_fast_clear.c
> +++ b/src/amd/vulkan/radv_meta_fast_clear.c
> @@ -623,10 +623,13 @@ radv_emit_color_decompress(struct radv_cmd_buffer *cmd_buffer,
>
> if (decompress_dcc && radv_image_has_dcc(image)) {
> pipeline = cmd_buffer->device->meta_state.fast_clear_flush.dcc_decompress_pipeline;
> + cmd_buffer->counters.counters[RADV_NUM_DCC_DECOMPRESSIONS]++;
> } else if (radv_image_has_fmask(image)) {
> pipeline = cmd_buffer->device->meta_state.fast_clear_flush.fmask_decompress_pipeline;
> + cmd_buffer->counters.counters[RADV_NUM_FMASK_DECOMPRESSIONS]++;
> } else {
> pipeline = cmd_buffer->device->meta_state.fast_clear_flush.cmask_eliminate_pipeline;
> + cmd_buffer->counters.counters[RADV_NUM_CMASK_ELIMINATES]++;
> }
>
> if (!decompress_dcc && radv_image_has_dcc(image)) {
> diff --git a/src/amd/vulkan/radv_meta_resolve.c b/src/amd/vulkan/radv_meta_resolve.c
> index 7ce36b1df6e..2f8011bfb46 100644
> --- a/src/amd/vulkan/radv_meta_resolve.c
> +++ b/src/amd/vulkan/radv_meta_resolve.c
> @@ -322,6 +322,8 @@ emit_resolve(struct radv_cmd_buffer *cmd_buffer,
>
> radv_CmdDraw(cmd_buffer_h, 3, 1, 0, 0);
> cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
> +
> + cmd_buffer->counters.counters[RADV_NUM_HW_RESOLVES]++;
> }
>
> enum radv_resolve_method {
> diff --git a/src/amd/vulkan/radv_meta_resolve_cs.c b/src/amd/vulkan/radv_meta_resolve_cs.c
> index e56df7f8a59..9cb43a1b83a 100644
> --- a/src/amd/vulkan/radv_meta_resolve_cs.c
> +++ b/src/amd/vulkan/radv_meta_resolve_cs.c
> @@ -399,6 +399,7 @@ emit_resolve(struct radv_cmd_buffer *cmd_buffer,
> push_constants);
> radv_unaligned_dispatch(cmd_buffer, resolve_extent->width, resolve_extent->height, 1);
>
> + cmd_buffer->counters.counters[RADV_NUM_CS_RESOLVES]++;
> }
>
> void radv_meta_resolve_compute_image(struct radv_cmd_buffer *cmd_buffer,
> diff --git a/src/amd/vulkan/radv_meta_resolve_fs.c b/src/amd/vulkan/radv_meta_resolve_fs.c
> index af4a6fe7a66..9205b0a76fa 100644
> --- a/src/amd/vulkan/radv_meta_resolve_fs.c
> +++ b/src/amd/vulkan/radv_meta_resolve_fs.c
> @@ -442,6 +442,8 @@ emit_resolve(struct radv_cmd_buffer *cmd_buffer,
>
> radv_CmdDraw(cmd_buffer_h, 3, 1, 0, 0);
> cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
> +
> + cmd_buffer->counters.counters[RADV_NUM_FS_RESOLVES]++;
> }
>
> void radv_meta_resolve_fragment_image(struct radv_cmd_buffer *cmd_buffer,
> diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
> index ac756f2c247..7cb8dbb75a0 100644
> --- a/src/amd/vulkan/radv_private.h
> +++ b/src/amd/vulkan/radv_private.h
> @@ -647,6 +647,51 @@ struct radv_bo_list {
> pthread_mutex_t mutex;
> };
>
> +enum radv_counter_id {
> + RADV_NUM_DRAW_CALLS,
> + RADV_NUM_DISPATCH_CALLS,
> + RADV_NUM_META_OPERATIONS,
> + RADV_NUM_CLEAR_ATTACHMENTS,
> + RADV_NUM_SLOW_COLOR_CLEARS,
> + RADV_NUM_FAST_COLOR_CLEARS,
> + RADV_NUM_SLOW_DEPTH_CLEARS,
> + RADV_NUM_FAST_DEPTH_CLEARS,
> + RADV_NUM_EMITTED_PIPELINES,
> + RADV_NUM_FLUSH_CONSTANTS,
> + RADV_NUM_FLUSH_DESCRIPTORS,
> + RADV_NUM_VB_UPDATES,
> + RADV_NUM_CMASK_INITS,
> + RADV_NUM_CMASK_ELIMINATES,
> + RADV_NUM_FMASK_DECOMPRESSIONS,
> + RADV_NUM_DCC_DECOMPRESSIONS,
> + RADV_NUM_DCC_INITS,
> + RADV_NUM_HTILE_INITS,
> + RADV_NUM_HTILE_DECOMPRESSIONS,
> + RADV_NUM_HW_RESOLVES,
> + RADV_NUM_FS_RESOLVES,
> + RADV_NUM_CS_RESOLVES,
> + RADV_NUM_CP_DMA_CLEARS,
> + RADV_NUM_CP_DMA_COPIES,
> + RADV_NUM_CS_CLEARS,
> + RADV_NUM_CS_COPIES,
> + RADV_NUM_UPDATE_BUFFERS,
> + RADV_NUM_B2I_COPIES,
> + RADV_NUM_I2B_COPIES,
> + RADV_NUM_IMAGE_COPIES,
> + RADV_NUM_VS_FLUSHES,
> + RADV_NUM_PS_FLUSHES,
> + RADV_NUM_CS_FLUSHES,
> + RADV_NUM_CB_FLUSHES,
> + RADV_NUM_CB_META_FLUSHES,
> + RADV_NUM_DB_FLUSHES,
> + RADV_NUM_DB_META_FLUSHES,
> + RADV_NUM_COUNTERS,
> +};
> +
> +struct radv_counters {
> + unsigned counters[RADV_NUM_COUNTERS];
> +};
> +
> struct radv_device {
> VK_LOADER_DATA _loader_data;
>
> @@ -716,6 +761,9 @@ struct radv_device {
>
> /* Whether anisotropy is forced with RADV_TEX_ANISO (-1 is disabled). */
> int force_aniso;
> +
> + /* Software counters. */
> + struct radv_counters counters;
> };
>
> struct radv_device_memory {
> @@ -1118,6 +1166,9 @@ struct radv_cmd_buffer {
> * Whether a query pool has been resetted and we have to flush caches.
> */
> bool pending_reset_query;
> +
> + /* Software counters. */
> + struct radv_counters counters;
> };
>
> struct radv_image;
> diff --git a/src/amd/vulkan/radv_wsi.c b/src/amd/vulkan/radv_wsi.c
> index 346fb43d675..22ce2c2864b 100644
> --- a/src/amd/vulkan/radv_wsi.c
> +++ b/src/amd/vulkan/radv_wsi.c
> @@ -248,11 +248,98 @@ VkResult radv_AcquireNextImage2KHR(
> return result;
> }
>
> +static void
> +radv_print_counters(struct radv_counters *counters)
> +{
> + FILE *f = fopen("/tmp/radv_counters", "w");
> +
> + fprintf(f, "num draw calls: %d\n",
> + counters->counters[RADV_NUM_DRAW_CALLS]);
> + fprintf(f, "num dispatch calls: %d\n",
> + counters->counters[RADV_NUM_DISPATCH_CALLS]);
> + fprintf(f, "num meta operations: %d\n",
> + counters->counters[RADV_NUM_META_OPERATIONS]);
> + fprintf(f, "num clear attachments: %d\n",
> + counters->counters[RADV_NUM_CLEAR_ATTACHMENTS]);
> + fprintf(f, "num slow color clears: %d\n",
> + counters->counters[RADV_NUM_SLOW_COLOR_CLEARS]);
> + fprintf(f, "num fast color clears: %d\n",
> + counters->counters[RADV_NUM_FAST_COLOR_CLEARS]);
> + fprintf(f, "num slow depth clears: %d\n",
> + counters->counters[RADV_NUM_SLOW_DEPTH_CLEARS]);
> + fprintf(f, "num fast depth clears: %d\n",
> + counters->counters[RADV_NUM_FAST_DEPTH_CLEARS]);
> + fprintf(f, "num emitted pipelines: %d\n",
> + counters->counters[RADV_NUM_EMITTED_PIPELINES]);
> + fprintf(f, "num flush constants: %d\n",
> + counters->counters[RADV_NUM_FLUSH_CONSTANTS]);
> + fprintf(f, "num flush descriptors: %d\n",
> + counters->counters[RADV_NUM_FLUSH_DESCRIPTORS]);
> + fprintf(f, "num VB updates: %d\n",
> + counters->counters[RADV_NUM_VB_UPDATES]);
> + fprintf(f, "num CMASK inits: %d\n",
> + counters->counters[RADV_NUM_CMASK_INITS]);
> + fprintf(f, "num CMASK eliminates: %d\n",
> + counters->counters[RADV_NUM_CMASK_ELIMINATES]);
> + fprintf(f, "num FMASK decompressions: %d\n",
> + counters->counters[RADV_NUM_FMASK_DECOMPRESSIONS]);
> + fprintf(f, "num DCC decompressions: %d\n",
> + counters->counters[RADV_NUM_DCC_DECOMPRESSIONS]);
> + fprintf(f, "num DCC inits: %d\n",
> + counters->counters[RADV_NUM_DCC_INITS]);
> + fprintf(f, "num HTILE inits: %d\n",
> + counters->counters[RADV_NUM_HTILE_INITS]);
> + fprintf(f, "num HTILE decompressions: %d\n",
> + counters->counters[RADV_NUM_HTILE_DECOMPRESSIONS]);
> + fprintf(f, "num HW resolves: %d\n",
> + counters->counters[RADV_NUM_HW_RESOLVES]);
> + fprintf(f, "num FS resolves: %d\n",
> + counters->counters[RADV_NUM_FS_RESOLVES]);
> + fprintf(f, "num CS resolves: %d\n",
> + counters->counters[RADV_NUM_CS_RESOLVES]);
> + fprintf(f, "num CP DMA clears: %d\n",
> + counters->counters[RADV_NUM_CP_DMA_CLEARS]);
> + fprintf(f, "num CP DMA copies: %d\n",
> + counters->counters[RADV_NUM_CP_DMA_COPIES]);
> + fprintf(f, "num CS clears: %d\n",
> + counters->counters[RADV_NUM_CS_CLEARS]);
> + fprintf(f, "num CS copies: %d\n",
> + counters->counters[RADV_NUM_CS_COPIES]);
> + fprintf(f, "num update buffers: %d\n",
> + counters->counters[RADV_NUM_UPDATE_BUFFERS]);
> + fprintf(f, "num B2I copies: %d\n",
> + counters->counters[RADV_NUM_B2I_COPIES]);
> + fprintf(f, "num I2B copies: %d\n",
> + counters->counters[RADV_NUM_I2B_COPIES]);
> + fprintf(f, "num image copies: %d\n",
> + counters->counters[RADV_NUM_IMAGE_COPIES]);
> + fprintf(f, "num VS flushes: %d\n",
> + counters->counters[RADV_NUM_VS_FLUSHES]);
> + fprintf(f, "num PS flushes: %d\n",
> + counters->counters[RADV_NUM_PS_FLUSHES]);
> + fprintf(f, "num CS flushes: %d\n",
> + counters->counters[RADV_NUM_CS_FLUSHES]);
> + fprintf(f, "num CB flushes: %d\n",
> + counters->counters[RADV_NUM_CB_FLUSHES]);
> + fprintf(f, "num CB meta flushes: %d\n",
> + counters->counters[RADV_NUM_CB_META_FLUSHES]);
> + fprintf(f, "num DB flushes: %d\n",
> + counters->counters[RADV_NUM_DB_FLUSHES]);
> + fprintf(f, "num DB meta flushes: %d\n",
> + counters->counters[RADV_NUM_DB_META_FLUSHES]);
> + fprintf(f, "\n\n");
> + fclose(f);
> +}
> +
> VkResult radv_QueuePresentKHR(
> VkQueue _queue,
> const VkPresentInfoKHR* pPresentInfo)
> {
> RADV_FROM_HANDLE(radv_queue, queue, _queue);
> +
> + radv_print_counters(&queue->device->counters);
> + memset(&queue->device->counters, 0, sizeof(queue->device->counters));
> +
> return wsi_common_queue_present(&queue->device->physical_device->wsi_device,
> radv_device_to_handle(queue->device),
> _queue,
> diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c
> index a9f25725415..5aeba6a7e99 100644
> --- a/src/amd/vulkan/si_cmd_buffer.c
> +++ b/src/amd/vulkan/si_cmd_buffer.c
> @@ -971,6 +971,21 @@ si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer)
> if (!cmd_buffer->state.flush_bits)
> return;
>
> + if (cmd_buffer->state.flush_bits & RADV_CMD_FLAG_VS_PARTIAL_FLUSH)
> + cmd_buffer->counters.counters[RADV_NUM_VS_FLUSHES]++;
> + if (cmd_buffer->state.flush_bits & RADV_CMD_FLAG_PS_PARTIAL_FLUSH)
> + cmd_buffer->counters.counters[RADV_NUM_PS_FLUSHES]++;
> + if (cmd_buffer->state.flush_bits & RADV_CMD_FLAG_CS_PARTIAL_FLUSH)
> + cmd_buffer->counters.counters[RADV_NUM_CS_FLUSHES]++;
> + if (cmd_buffer->state.flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB)
> + cmd_buffer->counters.counters[RADV_NUM_CB_FLUSHES]++;
> + if (cmd_buffer->state.flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB_META)
> + cmd_buffer->counters.counters[RADV_NUM_CB_META_FLUSHES]++;
> + if (cmd_buffer->state.flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB)
> + cmd_buffer->counters.counters[RADV_NUM_DB_FLUSHES]++;
> + if (cmd_buffer->state.flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB_META)
> + cmd_buffer->counters.counters[RADV_NUM_DB_META_FLUSHES]++;
> +
> enum chip_class chip_class = cmd_buffer->device->physical_device->rad_info.chip_class;
> radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 128);
>
> @@ -1244,6 +1259,8 @@ void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
> }
> if (realign_size)
> si_cp_dma_realign_engine(cmd_buffer, realign_size);
> +
> + cmd_buffer->counters.counters[RADV_NUM_CP_DMA_COPIES]++;
> }
>
> void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
> @@ -1271,6 +1288,8 @@ void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
> size -= byte_count;
> va += byte_count;
> }
> +
> + cmd_buffer->counters.counters[RADV_NUM_CP_DMA_CLEARS]++;
> }
>
> void si_cp_dma_wait_for_idle(struct radv_cmd_buffer *cmd_buffer)
>
More information about the mesa-dev
mailing list