[Mesa-dev] [PATCH] radeonsi: clean up primitive binning enablement

[Bas Nieuwenhuizen]

Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
On Sat, Nov 24, 2018 at 12:34 AM Marek Olšák <maraeo at gmail.com> wrote:
>
> From: Marek Olšák <marek.olsak at amd.com>
>
> no change in behavior.
> ---
>  src/gallium/drivers/radeonsi/si_pipe.c | 27 +++++++++++++++-----------
>  1 file changed, 16 insertions(+), 11 deletions(-)
>
> diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c
> index c487ef43b52..9080de1ceca 100644
> --- a/src/gallium/drivers/radeonsi/si_pipe.c
> +++ b/src/gallium/drivers/radeonsi/si_pipe.c
> @@ -1025,35 +1025,40 @@ struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws,
>         sscreen->clear_db_cache_before_clear =
>                 driQueryOptionb(config->options, "radeonsi_clear_db_cache_before_clear");
>         sscreen->has_msaa_sample_loc_bug = (sscreen->info.family >= CHIP_POLARIS10 &&
>                                             sscreen->info.family <= CHIP_POLARIS12) ||
>                                            sscreen->info.family == CHIP_VEGA10 ||
>                                            sscreen->info.family == CHIP_RAVEN;
>         sscreen->has_ls_vgpr_init_bug = sscreen->info.family == CHIP_VEGA10 ||
>                                         sscreen->info.family == CHIP_RAVEN;
>         sscreen->has_dcc_constant_encode = sscreen->info.family == CHIP_RAVEN2;
>
> +       /* Only enable primitive binning on APUs by default. */
> +       sscreen->dpbb_allowed = sscreen->info.family == CHIP_RAVEN ||
> +                               sscreen->info.family == CHIP_RAVEN2;
> +
> +       sscreen->dfsm_allowed = sscreen->info.family == CHIP_RAVEN ||
> +                               sscreen->info.family == CHIP_RAVEN2;
> +
> +       /* Process DPBB enable flags. */
>         if (sscreen->debug_flags & DBG(DPBB)) {
>                 sscreen->dpbb_allowed = true;
> -       } else {
> -               /* Only enable primitive binning on APUs by default. */
> -               /* TODO: Investigate if binning is profitable on Vega12. */
> -               sscreen->dpbb_allowed = !(sscreen->debug_flags & DBG(NO_DPBB)) &&
> -                                       (sscreen->info.family == CHIP_RAVEN ||
> -                                        sscreen->info.family == CHIP_RAVEN2);
> +               if (sscreen->debug_flags & DBG(DFSM))
> +                       sscreen->dfsm_allowed = true;
>         }
>
> -       if (sscreen->debug_flags & DBG(DFSM)) {
> -               sscreen->dfsm_allowed = sscreen->dpbb_allowed;
> -       } else {
> -               sscreen->dfsm_allowed = sscreen->dpbb_allowed &&
> -                                       !(sscreen->debug_flags & DBG(NO_DFSM));
> +       /* Process DPBB disable flags. */
> +       if (sscreen->debug_flags & DBG(NO_DPBB)) {
> +               sscreen->dpbb_allowed = false;
> +               sscreen->dfsm_allowed = false;
> +       } else if (sscreen->debug_flags & DBG(NO_DFSM)) {
> +               sscreen->dfsm_allowed = false;
>         }
>
>         /* While it would be nice not to have this flag, we are constrained
>          * by the reality that LLVM 5.0 doesn't have working VGPR indexing
>          * on GFX9.
>          */
>         sscreen->llvm_has_working_vgpr_indexing = sscreen->info.chip_class <= VI;
>
>         /* Some chips have RB+ registers, but don't support RB+. Those must
>          * always disable it.
> --
> 2.17.1
>
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