[Mesa-dev] [PATCH 3/3] radeonsi: add memory management stress tests for GDS

[Marek Olšák]

From: Marek Olšák <marek.olsak at amd.com>

---
 src/gallium/drivers/radeonsi/si_pipe.c | 46 ++++++++++++++++++++++++++
 src/gallium/drivers/radeonsi/si_pipe.h |  2 ++
 2 files changed, 48 insertions(+)

diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c
index 9080de1ceca..503d8331906 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -96,20 +96,22 @@ static const struct debug_named_value debug_options[] = {
 	{ "nodccmsaa", DBG(NO_DCC_MSAA), "Disable DCC for MSAA" },
 	{ "nofmask", DBG(NO_FMASK), "Disable MSAA compression" },
 
 	/* Tests: */
 	{ "testdma", DBG(TEST_DMA), "Invoke SDMA tests and exit." },
 	{ "testvmfaultcp", DBG(TEST_VMFAULT_CP), "Invoke a CP VM fault test and exit." },
 	{ "testvmfaultsdma", DBG(TEST_VMFAULT_SDMA), "Invoke a SDMA VM fault test and exit." },
 	{ "testvmfaultshader", DBG(TEST_VMFAULT_SHADER), "Invoke a shader VM fault test and exit." },
 	{ "testdmaperf", DBG(TEST_DMA_PERF), "Test DMA performance" },
 	{ "testgds", DBG(TEST_GDS), "Test GDS." },
+	{ "testgdsmm", DBG(TEST_GDS_MM), "Test GDS memory management." },
+	{ "testgdsoamm", DBG(TEST_GDS_OA_MM), "Test GDS OA memory management." },
 
 	DEBUG_NAMED_VALUE_END /* must be last */
 };
 
 static void si_init_compiler(struct si_screen *sscreen,
 			     struct ac_llvm_compiler *compiler)
 {
 	/* Only create the less-optimizing version of the compiler on APUs
 	 * predating Ryzen (Raven). */
 	bool create_low_opt_compiler = !sscreen->info.has_dedicated_vram &&
@@ -781,20 +783,55 @@ static void si_test_vmfault(struct si_screen *sscreen)
 		ctx->flush(ctx, NULL, 0);
 		puts("VM fault test: SDMA - done.");
 	}
 	if (sscreen->debug_flags & DBG(TEST_VMFAULT_SHADER)) {
 		util_test_constant_buffer(ctx, buf);
 		puts("VM fault test: Shader - done.");
 	}
 	exit(0);
 }
 
+static void si_test_gds_memory_management(struct si_context *sctx,
+					  unsigned alloc_size, unsigned alignment,
+					  enum radeon_bo_domain domain)
+{
+	struct radeon_winsys *ws = sctx->ws;
+	struct radeon_cmdbuf *cs[8];
+	struct pb_buffer *gds_bo[ARRAY_SIZE(cs)];
+
+	for (unsigned i = 0; i < ARRAY_SIZE(cs); i++) {
+		cs[i] = ws->cs_create(sctx->ctx, RING_COMPUTE,
+				      NULL, NULL, false);
+		gds_bo[i] = ws->buffer_create(ws, alloc_size, alignment, domain, 0);
+		assert(gds_bo[i]);
+	}
+
+	for (unsigned iterations = 0; iterations < 20000; iterations++) {
+		for (unsigned i = 0; i < ARRAY_SIZE(cs); i++) {
+			/* This clears GDS with CP DMA.
+			 *
+			 * We don't care if GDS is present. Just add some packet
+			 * to make the GPU busy for a moment.
+			 */
+			si_cp_dma_clear_buffer(sctx, cs[i], NULL, 0, alloc_size, 0,
+					       SI_CPDMA_SKIP_BO_LIST_UPDATE |
+					       SI_CPDMA_SKIP_CHECK_CS_SPACE |
+					       SI_CPDMA_SKIP_GFX_SYNC, 0, 0);
+
+			ws->cs_add_buffer(cs[i], gds_bo[i], domain,
+					  RADEON_USAGE_READWRITE, 0);
+			ws->cs_flush(cs[i], PIPE_FLUSH_ASYNC, NULL);
+		}
+	}
+	exit(0);
+}
+
 static void si_disk_cache_create(struct si_screen *sscreen)
 {
 	/* Don't use the cache if shader dumping is enabled. */
 	if (sscreen->debug_flags & DBG_ALL_SHADERS)
 		return;
 
 	struct mesa_sha1 ctx;
 	unsigned char sha1[20];
 	char cache_id[20 * 2 + 1];
 
@@ -1135,12 +1172,21 @@ struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws,
 	}
 
 	if (sscreen->debug_flags & (DBG(TEST_VMFAULT_CP) |
 				      DBG(TEST_VMFAULT_SDMA) |
 				      DBG(TEST_VMFAULT_SHADER)))
 		si_test_vmfault(sscreen);
 
 	if (sscreen->debug_flags & DBG(TEST_GDS))
 		si_test_gds((struct si_context*)sscreen->aux_context);
 
+	if (sscreen->debug_flags & DBG(TEST_GDS_MM)) {
+		si_test_gds_memory_management((struct si_context*)sscreen->aux_context,
+					      32 * 1024, 4, RADEON_DOMAIN_GDS);
+	}
+	if (sscreen->debug_flags & DBG(TEST_GDS_OA_MM)) {
+		si_test_gds_memory_management((struct si_context*)sscreen->aux_context,
+					      4, 1, RADEON_DOMAIN_OA);
+	}
+
 	return &sscreen->b;
 }
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h
index 3ec645f9c71..1d677d29e88 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -167,20 +167,22 @@ enum {
 	DBG_NO_DCC_MSAA,
 	DBG_NO_FMASK,
 
 	/* Tests: */
 	DBG_TEST_DMA,
 	DBG_TEST_VMFAULT_CP,
 	DBG_TEST_VMFAULT_SDMA,
 	DBG_TEST_VMFAULT_SHADER,
 	DBG_TEST_DMA_PERF,
 	DBG_TEST_GDS,
+	DBG_TEST_GDS_MM,
+	DBG_TEST_GDS_OA_MM,
 };
 
 #define DBG_ALL_SHADERS		(((1 << (DBG_CS + 1)) - 1))
 #define DBG(name)		(1ull << DBG_##name)
 
 enum si_cache_policy {
 	L2_BYPASS,
 	L2_STREAM, /* same as SLC=1 */
 	L2_LRU,    /* same as SLC=0 */
 };
-- 
2.17.1