[Mesa-dev] [PATCH 08/15] radeonsi: add GDS support to CP DMA
Samuel Pitoiset
samuel.pitoiset at gmail.com
Thu Oct 4 07:27:15 UTC 2018
Did you benchmark copies and clears with GDS?
On 10/3/18 12:35 AM, Marek Olšák wrote:
> From: Marek Olšák <marek.olsak at amd.com>
>
> ---
> src/gallium/drivers/radeonsi/si_cp_dma.c | 104 ++++++++++++++++++-----
> src/gallium/drivers/radeonsi/si_pipe.c | 4 +
> src/gallium/drivers/radeonsi/si_pipe.h | 2 +
> 3 files changed, 89 insertions(+), 21 deletions(-)
>
> diff --git a/src/gallium/drivers/radeonsi/si_cp_dma.c b/src/gallium/drivers/radeonsi/si_cp_dma.c
> index e85bb9b1acf..c1ecd5fb3e8 100644
> --- a/src/gallium/drivers/radeonsi/si_cp_dma.c
> +++ b/src/gallium/drivers/radeonsi/si_cp_dma.c
> @@ -32,22 +32,24 @@
> #define CP_DMA_CLEAR_PERF_THRESHOLD (32 * 1024) /* guess (clear is much slower) */
>
> /* Set this if you want the ME to wait until CP DMA is done.
> * It should be set on the last CP DMA packet. */
> #define CP_DMA_SYNC (1 << 0)
>
> /* Set this if the source data was used as a destination in a previous CP DMA
> * packet. It's for preventing a read-after-write (RAW) hazard between two
> * CP DMA packets. */
> #define CP_DMA_RAW_WAIT (1 << 1)
> +#define CP_DMA_DST_IS_GDS (1 << 2)
> #define CP_DMA_CLEAR (1 << 3)
> #define CP_DMA_PFP_SYNC_ME (1 << 4)
> +#define CP_DMA_SRC_IS_GDS (1 << 5)
>
> /* The max number of bytes that can be copied per packet. */
> static inline unsigned cp_dma_max_byte_count(struct si_context *sctx)
> {
> unsigned max = sctx->chip_class >= GFX9 ?
> S_414_BYTE_COUNT_GFX9(~0u) :
> S_414_BYTE_COUNT_GFX6(~0u);
>
> /* make it aligned for optimal performance */
> return max & ~(SI_CPDMA_ALIGNMENT - 1);
> @@ -83,27 +85,37 @@ static void si_emit_cp_dma(struct si_context *sctx, uint64_t dst_va,
> command |= S_414_DISABLE_WR_CONFIRM_GFX6(1);
> }
>
> if (flags & CP_DMA_RAW_WAIT)
> command |= S_414_RAW_WAIT(1);
>
> /* Src and dst flags. */
> if (sctx->chip_class >= GFX9 && !(flags & CP_DMA_CLEAR) &&
> src_va == dst_va) {
> header |= S_411_DST_SEL(V_411_NOWHERE); /* prefetch only */
> + } else if (flags & CP_DMA_DST_IS_GDS) {
> + header |= S_411_DST_SEL(V_411_GDS);
> + /* GDS increments the address, not CP. */
> + command |= S_414_DAS(V_414_REGISTER) |
> + S_414_DAIC(V_414_NO_INCREMENT);
> } else if (sctx->chip_class >= CIK && cache_policy != L2_BYPASS) {
> header |= S_411_DST_SEL(V_411_DST_ADDR_TC_L2) |
> S_500_DST_CACHE_POLICY(cache_policy == L2_STREAM);
> }
>
> if (flags & CP_DMA_CLEAR) {
> header |= S_411_SRC_SEL(V_411_DATA);
> + } else if (flags & CP_DMA_SRC_IS_GDS) {
> + header |= S_411_SRC_SEL(V_411_GDS);
> + /* Both of these are required for GDS. It does increment the address. */
> + command |= S_414_SAS(V_414_REGISTER) |
> + S_414_SAIC(V_414_NO_INCREMENT);
> } else if (sctx->chip_class >= CIK && cache_policy != L2_BYPASS) {
> header |= S_411_SRC_SEL(V_411_SRC_ADDR_TC_L2) |
> S_500_SRC_CACHE_POLICY(cache_policy == L2_STREAM);
> }
>
> if (sctx->chip_class >= CIK) {
> radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, 0));
> radeon_emit(cs, header);
> radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */
> radeon_emit(cs, src_va >> 32); /* SRC_ADDR_HI [31:0] */
> @@ -179,33 +191,35 @@ static void si_cp_dma_prepare(struct si_context *sctx, struct pipe_resource *dst
> unsigned *packet_flags)
> {
> /* Fast exit for a CPDMA prefetch. */
> if ((user_flags & SI_CPDMA_SKIP_ALL) == SI_CPDMA_SKIP_ALL) {
> *is_first = false;
> return;
> }
>
> if (!(user_flags & SI_CPDMA_SKIP_BO_LIST_UPDATE)) {
> /* Count memory usage in so that need_cs_space can take it into account. */
> - si_context_add_resource_size(sctx, dst);
> + if (dst)
> + si_context_add_resource_size(sctx, dst);
> if (src)
> si_context_add_resource_size(sctx, src);
> }
>
> if (!(user_flags & SI_CPDMA_SKIP_CHECK_CS_SPACE))
> si_need_gfx_cs_space(sctx);
>
> /* This must be done after need_cs_space. */
> if (!(user_flags & SI_CPDMA_SKIP_BO_LIST_UPDATE)) {
> - radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
> - r600_resource(dst),
> - RADEON_USAGE_WRITE, RADEON_PRIO_CP_DMA);
> + if (dst)
> + radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
> + r600_resource(dst),
> + RADEON_USAGE_WRITE, RADEON_PRIO_CP_DMA);
> if (src)
> radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
> r600_resource(src),
> RADEON_USAGE_READ, RADEON_PRIO_CP_DMA);
> }
>
> /* Flush the caches for the first copy only.
> * Also wait for the previous CP DMA operations.
> */
> if (!(user_flags & SI_CPDMA_SKIP_GFX_SYNC) && sctx->flags)
> @@ -227,57 +241,59 @@ static void si_cp_dma_prepare(struct si_context *sctx, struct pipe_resource *dst
> *packet_flags |= CP_DMA_PFP_SYNC_ME;
> }
> }
>
> void si_cp_dma_clear_buffer(struct si_context *sctx, struct pipe_resource *dst,
> uint64_t offset, uint64_t size, unsigned value,
> enum si_coherency coher,
> enum si_cache_policy cache_policy)
> {
> struct r600_resource *rdst = r600_resource(dst);
> - uint64_t va = rdst->gpu_address + offset;
> + uint64_t va = (rdst ? rdst->gpu_address : 0) + offset;
> bool is_first = true;
>
> assert(size && size % 4 == 0);
>
> /* Mark the buffer range of destination as valid (initialized),
> * so that transfer_map knows it should wait for the GPU when mapping
> * that range. */
> - util_range_add(&rdst->valid_buffer_range, offset, offset + size);
> + if (rdst)
> + util_range_add(&rdst->valid_buffer_range, offset, offset + size);
>
> /* Flush the caches. */
> sctx->flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
> SI_CONTEXT_CS_PARTIAL_FLUSH |
> get_flush_flags(sctx, coher, cache_policy);
>
> while (size) {
> unsigned byte_count = MIN2(size, cp_dma_max_byte_count(sctx));
> - unsigned dma_flags = CP_DMA_CLEAR;
> + unsigned dma_flags = CP_DMA_CLEAR | (rdst ? 0 : CP_DMA_DST_IS_GDS);
>
> si_cp_dma_prepare(sctx, dst, NULL, byte_count, size, 0, coher,
> &is_first, &dma_flags);
>
> /* Emit the clear packet. */
> si_emit_cp_dma(sctx, va, value, byte_count, dma_flags, cache_policy);
>
> size -= byte_count;
> va += byte_count;
> }
>
> - if (cache_policy != L2_BYPASS)
> + if (rdst && cache_policy != L2_BYPASS)
> rdst->TC_L2_dirty = true;
>
> /* If it's not a framebuffer fast clear... */
> if (coher == SI_COHERENCY_SHADER)
> sctx->num_cp_dma_calls++;
> }
>
> +/* dst == NULL means GDS. */
> void si_clear_buffer(struct si_context *sctx, struct pipe_resource *dst,
> uint64_t offset, uint64_t size, unsigned value,
> enum si_coherency coher)
> {
> struct radeon_winsys *ws = sctx->ws;
> struct r600_resource *rdst = r600_resource(dst);
> enum si_cache_policy cache_policy = get_cache_policy(sctx, coher);
> uint64_t dma_clear_size;
>
> if (!size)
> @@ -311,20 +327,21 @@ void si_clear_buffer(struct si_context *sctx, struct pipe_resource *dst,
>
> offset += dma_clear_size;
> size -= dma_clear_size;
> }
>
> if (size) {
> /* Handle non-dword alignment.
> *
> * This function is called for embedded texture metadata clears,
> * but those should always be properly aligned. */
> + assert(dst);
> assert(dst->target == PIPE_BUFFER);
> assert(size < 4);
>
> pipe_buffer_write(&sctx->b, dst, offset, size, &value);
> }
> }
>
> static void si_pipe_clear_buffer(struct pipe_context *ctx,
> struct pipe_resource *dst,
> unsigned offset, unsigned size,
> @@ -423,99 +440,108 @@ static void si_cp_dma_realign_engine(struct si_context *sctx, unsigned size,
> &sctx->scratch_buffer->b.b, size, size, user_flags,
> coher, is_first, &dma_flags);
>
> va = sctx->scratch_buffer->gpu_address;
> si_emit_cp_dma(sctx, va, va + SI_CPDMA_ALIGNMENT, size, dma_flags,
> cache_policy);
> }
>
> /**
> * Do memcpy between buffers using CP DMA.
> + * If src or dst is NULL, it means read or write GDS, respectively.
> *
> * \param user_flags bitmask of SI_CPDMA_*
> */
> void si_cp_dma_copy_buffer(struct si_context *sctx,
> struct pipe_resource *dst, struct pipe_resource *src,
> uint64_t dst_offset, uint64_t src_offset, unsigned size,
> unsigned user_flags, enum si_coherency coher,
> enum si_cache_policy cache_policy)
> {
> uint64_t main_dst_offset, main_src_offset;
> unsigned skipped_size = 0;
> unsigned realign_size = 0;
> + unsigned gds_flags = (dst ? 0 : CP_DMA_DST_IS_GDS) |
> + (src ? 0 : CP_DMA_SRC_IS_GDS);
> bool is_first = true;
>
> assert(size);
>
> - if (dst != src || dst_offset != src_offset) {
> - /* Mark the buffer range of destination as valid (initialized),
> - * so that transfer_map knows it should wait for the GPU when mapping
> - * that range. */
> - util_range_add(&r600_resource(dst)->valid_buffer_range, dst_offset,
> - dst_offset + size);
> - }
> + if (dst) {
> + /* Skip this for the L2 prefetch. */
> + if (dst != src || dst_offset != src_offset) {
> + /* Mark the buffer range of destination as valid (initialized),
> + * so that transfer_map knows it should wait for the GPU when mapping
> + * that range. */
> + util_range_add(&r600_resource(dst)->valid_buffer_range, dst_offset,
> + dst_offset + size);
> + }
>
> - dst_offset += r600_resource(dst)->gpu_address;
> - src_offset += r600_resource(src)->gpu_address;
> + dst_offset += r600_resource(dst)->gpu_address;
> + }
> + if (src)
> + src_offset += r600_resource(src)->gpu_address;
>
> /* The workarounds aren't needed on Fiji and beyond. */
> if (sctx->family <= CHIP_CARRIZO ||
> sctx->family == CHIP_STONEY) {
> /* If the size is not aligned, we must add a dummy copy at the end
> * just to align the internal counter. Otherwise, the DMA engine
> * would slow down by an order of magnitude for following copies.
> */
> if (size % SI_CPDMA_ALIGNMENT)
> realign_size = SI_CPDMA_ALIGNMENT - (size % SI_CPDMA_ALIGNMENT);
>
> /* If the copy begins unaligned, we must start copying from the next
> * aligned block and the skipped part should be copied after everything
> * else has been copied. Only the src alignment matters, not dst.
> + *
> + * GDS doesn't need the source address to be aligned.
> */
> - if (src_offset % SI_CPDMA_ALIGNMENT) {
> + if (src && src_offset % SI_CPDMA_ALIGNMENT) {
> skipped_size = SI_CPDMA_ALIGNMENT - (src_offset % SI_CPDMA_ALIGNMENT);
> /* The main part will be skipped if the size is too small. */
> skipped_size = MIN2(skipped_size, size);
> size -= skipped_size;
> }
> }
>
> /* Flush the caches. */
> - if (!(user_flags & SI_CPDMA_SKIP_GFX_SYNC)) {
> + if ((dst || src) && !(user_flags & SI_CPDMA_SKIP_GFX_SYNC)) {
> sctx->flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
> SI_CONTEXT_CS_PARTIAL_FLUSH |
> get_flush_flags(sctx, coher, cache_policy);
> }
>
> /* This is the main part doing the copying. Src is always aligned. */
> main_dst_offset = dst_offset + skipped_size;
> main_src_offset = src_offset + skipped_size;
>
> while (size) {
> unsigned byte_count = MIN2(size, cp_dma_max_byte_count(sctx));
> - unsigned dma_flags = 0;
> + unsigned dma_flags = gds_flags;
>
> si_cp_dma_prepare(sctx, dst, src, byte_count,
> size + skipped_size + realign_size,
> user_flags, coher, &is_first, &dma_flags);
>
> si_emit_cp_dma(sctx, main_dst_offset, main_src_offset,
> byte_count, dma_flags, cache_policy);
>
> size -= byte_count;
> main_src_offset += byte_count;
> main_dst_offset += byte_count;
> }
>
> /* Copy the part we skipped because src wasn't aligned. */
> if (skipped_size) {
> - unsigned dma_flags = 0;
> + unsigned dma_flags = gds_flags;
>
> si_cp_dma_prepare(sctx, dst, src, skipped_size,
> skipped_size + realign_size, user_flags,
> coher, &is_first, &dma_flags);
>
> si_emit_cp_dma(sctx, dst_offset, src_offset, skipped_size,
> dma_flags, cache_policy);
> }
>
> /* Finally, realign the engine if the size wasn't aligned. */
> @@ -676,14 +702,50 @@ void cik_emit_prefetch_L2(struct si_context *sctx, bool vertex_stage_only)
> }
> }
> }
>
> if (mask & SI_PREFETCH_PS)
> cik_prefetch_shader_async(sctx, sctx->queued.named.ps);
>
> sctx->prefetch_L2_mask = 0;
> }
>
> +void si_test_gds(struct si_context *sctx)
> +{
> + struct pipe_context *ctx = &sctx->b;
> + struct pipe_resource *src, *dst;
> + unsigned r[4] = {};
> + unsigned offset = debug_get_num_option("OFFSET", 16);
> +
> + src = pipe_buffer_create(ctx->screen, 0, PIPE_USAGE_DEFAULT, 16);
> + dst = pipe_buffer_create(ctx->screen, 0, PIPE_USAGE_DEFAULT, 16);
> + si_cp_dma_clear_buffer(sctx, src, 0, 4, 0xabcdef01, SI_COHERENCY_SHADER, L2_BYPASS);
> + si_cp_dma_clear_buffer(sctx, src, 4, 4, 0x23456789, SI_COHERENCY_SHADER, L2_BYPASS);
> + si_cp_dma_clear_buffer(sctx, src, 8, 4, 0x87654321, SI_COHERENCY_SHADER, L2_BYPASS);
> + si_cp_dma_clear_buffer(sctx, src, 12, 4, 0xfedcba98, SI_COHERENCY_SHADER, L2_BYPASS);
> + si_cp_dma_clear_buffer(sctx, dst, 0, 16, 0xdeadbeef, SI_COHERENCY_SHADER, L2_BYPASS);
> +
> + si_cp_dma_copy_buffer(sctx, NULL, src, offset, 0, 16, 0, SI_COHERENCY_NONE, L2_BYPASS);
> + si_cp_dma_copy_buffer(sctx, dst, NULL, 0, offset, 16, 0, SI_COHERENCY_NONE, L2_BYPASS);
> +
> + pipe_buffer_read(ctx, dst, 0, sizeof(r), r);
> + printf("GDS copy = %08x %08x %08x %08x -> %s\n", r[0], r[1], r[2], r[3],
> + r[0] == 0xabcdef01 && r[1] == 0x23456789 &&
> + r[2] == 0x87654321 && r[3] == 0xfedcba98 ? "pass" : "fail");
> +
> + si_cp_dma_clear_buffer(sctx, NULL, offset, 16, 0xc1ea4146, SI_COHERENCY_NONE, L2_BYPASS);
> + si_cp_dma_copy_buffer(sctx, dst, NULL, 0, offset, 16, 0, SI_COHERENCY_NONE, L2_BYPASS);
> +
> + pipe_buffer_read(ctx, dst, 0, sizeof(r), r);
> + printf("GDS clear = %08x %08x %08x %08x -> %s\n", r[0], r[1], r[2], r[3],
> + r[0] == 0xc1ea4146 && r[1] == 0xc1ea4146 &&
> + r[2] == 0xc1ea4146 && r[3] == 0xc1ea4146 ? "pass" : "fail");
> +
> + pipe_resource_reference(&src, NULL);
> + pipe_resource_reference(&dst, NULL);
> + exit(0);
> +}
> +
> void si_init_cp_dma_functions(struct si_context *sctx)
> {
> sctx->b.clear_buffer = si_pipe_clear_buffer;
> }
> diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c
> index aa5340668f9..c0b23ee5f6e 100644
> --- a/src/gallium/drivers/radeonsi/si_pipe.c
> +++ b/src/gallium/drivers/radeonsi/si_pipe.c
> @@ -95,20 +95,21 @@ static const struct debug_named_value debug_options[] = {
> { "nodccfb", DBG(NO_DCC_FB), "Disable separate DCC on the main framebuffer" },
> { "nodccmsaa", DBG(NO_DCC_MSAA), "Disable DCC for MSAA" },
> { "nofmask", DBG(NO_FMASK), "Disable MSAA compression" },
>
> /* Tests: */
> { "testdma", DBG(TEST_DMA), "Invoke SDMA tests and exit." },
> { "testvmfaultcp", DBG(TEST_VMFAULT_CP), "Invoke a CP VM fault test and exit." },
> { "testvmfaultsdma", DBG(TEST_VMFAULT_SDMA), "Invoke a SDMA VM fault test and exit." },
> { "testvmfaultshader", DBG(TEST_VMFAULT_SHADER), "Invoke a shader VM fault test and exit." },
> { "testdmaperf", DBG(TEST_DMA_PERF), "Test DMA performance" },
> + { "testgds", DBG(TEST_GDS), "Test GDS." },
>
> DEBUG_NAMED_VALUE_END /* must be last */
> };
>
> static void si_init_compiler(struct si_screen *sscreen,
> struct ac_llvm_compiler *compiler)
> {
> /* Only create the less-optimizing version of the compiler on APUs
> * predating Ryzen (Raven). */
> bool create_low_opt_compiler = !sscreen->info.has_dedicated_vram &&
> @@ -1089,12 +1090,15 @@ struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws,
>
> if (sscreen->debug_flags & DBG(TEST_DMA_PERF)) {
> si_test_dma_perf(sscreen);
> }
>
> if (sscreen->debug_flags & (DBG(TEST_VMFAULT_CP) |
> DBG(TEST_VMFAULT_SDMA) |
> DBG(TEST_VMFAULT_SHADER)))
> si_test_vmfault(sscreen);
>
> + if (sscreen->debug_flags & DBG(TEST_GDS))
> + si_test_gds((struct si_context*)sscreen->aux_context);
> +
> return &sscreen->b;
> }
> diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h
> index bb851374c54..dad3029bc31 100644
> --- a/src/gallium/drivers/radeonsi/si_pipe.h
> +++ b/src/gallium/drivers/radeonsi/si_pipe.h
> @@ -159,20 +159,21 @@ enum {
> DBG_NO_DCC_FB,
> DBG_NO_DCC_MSAA,
> DBG_NO_FMASK,
>
> /* Tests: */
> DBG_TEST_DMA,
> DBG_TEST_VMFAULT_CP,
> DBG_TEST_VMFAULT_SDMA,
> DBG_TEST_VMFAULT_SHADER,
> DBG_TEST_DMA_PERF,
> + DBG_TEST_GDS,
> };
>
> #define DBG_ALL_SHADERS (((1 << (DBG_CS + 1)) - 1))
> #define DBG(name) (1ull << DBG_##name)
>
> struct si_compute;
> struct hash_table;
> struct u_suballocator;
>
> /* Only 32-bit buffer allocations are supported, gallium doesn't support more
> @@ -1131,20 +1132,21 @@ void si_cp_dma_copy_buffer(struct si_context *sctx,
> struct pipe_resource *dst, struct pipe_resource *src,
> uint64_t dst_offset, uint64_t src_offset, unsigned size,
> unsigned user_flags, enum si_coherency coher,
> enum si_cache_policy cache_policy);
> void si_copy_buffer(struct si_context *sctx,
> struct pipe_resource *dst, struct pipe_resource *src,
> uint64_t dst_offset, uint64_t src_offset, unsigned size);
> void cik_prefetch_TC_L2_async(struct si_context *sctx, struct pipe_resource *buf,
> uint64_t offset, unsigned size);
> void cik_emit_prefetch_L2(struct si_context *sctx, bool vertex_stage_only);
> +void si_test_gds(struct si_context *sctx);
> void si_init_cp_dma_functions(struct si_context *sctx);
>
> /* si_debug.c */
> void si_save_cs(struct radeon_winsys *ws, struct radeon_cmdbuf *cs,
> struct radeon_saved_cs *saved, bool get_buffer_list);
> void si_clear_saved_cs(struct radeon_saved_cs *saved);
> void si_destroy_saved_cs(struct si_saved_cs *scs);
> void si_auto_log_cs(void *data, struct u_log_context *log);
> void si_log_hw_flush(struct si_context *sctx);
> void si_log_draw_state(struct si_context *sctx, struct u_log_context *log);
>
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