[Mesa-dev] [PATCH v2 10/32] intel/isl: Use the tile size for computing standard Y alignments
Jason Ekstrand
jason at jlekstrand.net
Fri Oct 12 18:46:40 UTC 2018
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
---
src/intel/isl/isl_gen9.c | 85 +++++-----------------------------------
1 file changed, 9 insertions(+), 76 deletions(-)
diff --git a/src/intel/isl/isl_gen9.c b/src/intel/isl/isl_gen9.c
index 8e460430a1c..f9d391ab67d 100644
--- a/src/intel/isl/isl_gen9.c
+++ b/src/intel/isl/isl_gen9.c
@@ -25,77 +25,6 @@
#include "isl_gen9.h"
#include "isl_priv.h"
-/**
- * Calculate the surface's subimage alignment, in units of surface samples,
- * for the standard tiling formats Yf and Ys.
- */
-static void
-gen9_calc_std_image_alignment_sa(const struct isl_device *dev,
- const struct isl_surf_init_info *restrict info,
- enum isl_tiling tiling,
- enum isl_msaa_layout msaa_layout,
- struct isl_extent3d *align_sa)
-{
- const struct isl_format_layout *fmtl = isl_format_get_layout(info->format);
-
- assert(isl_tiling_is_std_y(tiling));
-
- const uint32_t bpb = fmtl->bpb;
- const uint32_t is_Ys = tiling == ISL_TILING_GEN9_Ys;
-
- switch (info->dim) {
- case ISL_SURF_DIM_1D:
- /* See the Skylake BSpec > Memory Views > Common Surface Formats > Surface
- * Layout and Tiling > 1D Surfaces > 1D Alignment Requirements.
- */
- *align_sa = (struct isl_extent3d) {
- .w = 1 << (12 - (ffs(bpb) - 4) + (4 * is_Ys)),
- .h = 1,
- .d = 1,
- };
- return;
- case ISL_SURF_DIM_2D:
- /* See the Skylake BSpec > Memory Views > Common Surface Formats >
- * Surface Layout and Tiling > 2D Surfaces > 2D/CUBE Alignment
- * Requirements.
- */
- *align_sa = (struct isl_extent3d) {
- .w = 1 << (6 - ((ffs(bpb) - 4) / 2) + (4 * is_Ys)),
- .h = 1 << (6 - ((ffs(bpb) - 3) / 2) + (4 * is_Ys)),
- .d = 1,
- };
-
- if (is_Ys) {
- /* FINISHME(chadv): I don't trust this code. Untested. */
- isl_finishme("%s:%s: [SKL+] multisample TileYs", __FILE__, __func__);
-
- switch (msaa_layout) {
- case ISL_MSAA_LAYOUT_NONE:
- case ISL_MSAA_LAYOUT_INTERLEAVED:
- break;
- case ISL_MSAA_LAYOUT_ARRAY:
- align_sa->w >>= (ffs(info->samples) - 0) / 2;
- align_sa->h >>= (ffs(info->samples) - 1) / 2;
- break;
- }
- }
- return;
-
- case ISL_SURF_DIM_3D:
- /* See the Skylake BSpec > Memory Views > Common Surface Formats > Surface
- * Layout and Tiling > 1D Surfaces > 1D Alignment Requirements.
- */
- *align_sa = (struct isl_extent3d) {
- .w = 1 << (4 - ((ffs(bpb) - 2) / 3) + (4 * is_Ys)),
- .h = 1 << (4 - ((ffs(bpb) - 4) / 3) + (2 * is_Ys)),
- .d = 1 << (4 - ((ffs(bpb) - 3) / 3) + (2 * is_Ys)),
- };
- return;
- }
-
- unreachable("bad isl_surface_type");
-}
-
void
isl_gen9_choose_image_alignment_el(const struct isl_device *dev,
const struct isl_surf_init_info *restrict info,
@@ -166,11 +95,15 @@ isl_gen9_choose_image_alignment_el(const struct isl_device *dev,
*/
if (isl_tiling_is_std_y(tiling)) {
- struct isl_extent3d image_align_sa;
- gen9_calc_std_image_alignment_sa(dev, info, tiling, msaa_layout,
- &image_align_sa);
-
- *image_align_el = isl_extent3d_sa_to_el(info->format, image_align_sa);
+ /* Ys and Yf tiled images are aligned to the tile size */
+ struct isl_tile_info tile_info;
+ isl_tiling_get_info(tiling, info->dim, fmtl->bpb,
+ info->samples, &tile_info);
+ *image_align_el = (struct isl_extent3d) {
+ .w = tile_info.logical_extent_el.w,
+ .h = tile_info.logical_extent_el.h,
+ .d = tile_info.logical_extent_el.d,
+ };
return;
}
--
2.19.1
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