[Mesa-dev] [PATCH 2/3] anv: Implement VK_KHR_draw_indirect_count for gen 7

[Danylo Piliaiev]

Without MI_MATH we are forced to load MI_PREDICATE_SRC0
from memory on every predicate emission.

Signed-off-by: Danylo Piliaiev <danylo.piliaiev at globallogic.com>
---
 src/intel/vulkan/anv_extensions.py |  2 +-
 src/intel/vulkan/genX_cmd_buffer.c | 12 ++++++++++--
 2 files changed, 11 insertions(+), 3 deletions(-)

diff --git a/src/intel/vulkan/anv_extensions.py b/src/intel/vulkan/anv_extensions.py
index 7f44da6648..c13ce531ee 100644
--- a/src/intel/vulkan/anv_extensions.py
+++ b/src/intel/vulkan/anv_extensions.py
@@ -113,7 +113,7 @@ EXTENSIONS = [
     Extension('VK_KHR_xlib_surface',                      6, 'VK_USE_PLATFORM_XLIB_KHR'),
     Extension('VK_KHR_multiview',                         1, True),
     Extension('VK_KHR_display',                          23, 'VK_USE_PLATFORM_DISPLAY_KHR'),
-    Extension('VK_KHR_draw_indirect_count',               1, 'device->info.gen >= 8 || device->info.is_haswell'),
+    Extension('VK_KHR_draw_indirect_count',               1, True),
     Extension('VK_EXT_acquire_xlib_display',              1, 'VK_USE_PLATFORM_XLIB_XRANDR_EXT'),
     Extension('VK_EXT_debug_report',                      8, True),
     Extension('VK_EXT_direct_mode_display',               1, 'VK_USE_PLATFORM_DISPLAY_KHR'),
diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c
index d7b94efd19..f07a6aa7c9 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -2982,7 +2982,6 @@ void genX(CmdDrawIndexedIndirect)(
    }
 }
 
-#if GEN_IS_HASWELL || GEN_GEN >= 8
 static void
 emit_draw_count_predicate(struct anv_cmd_buffer *cmd_buffer,
                           struct anv_address count_address,
@@ -2991,7 +2990,13 @@ emit_draw_count_predicate(struct anv_cmd_buffer *cmd_buffer,
    /* Upload the current draw count from the draw parameters buffer to
     * MI_PREDICATE_SRC0.
     */
+#if GEN_GEN >= 8 || GEN_IS_HASWELL
    emit_lrr(&cmd_buffer->batch, MI_PREDICATE_SRC0, CS_GPR(MI_ALU_REG14));
+#else
+   emit_lrm(&cmd_buffer->batch, MI_PREDICATE_SRC0, count_address);
+   /* Zero the top 32-bits of MI_PREDICATE_SRC0 */
+   emit_lri(&cmd_buffer->batch, MI_PREDICATE_SRC0 + 4, 0);
+#endif
 
    /* Upload the index of the current primitive to MI_PREDICATE_SRC1. */
    emit_lri(&cmd_buffer->batch, MI_PREDICATE_SRC1, draw_index);
@@ -3050,8 +3055,10 @@ void genX(CmdDrawIndirectCountKHR)(
      pc.PipeControlFlushEnable = true;
    }
 
+#if GEN_GEN >= 8 || GEN_IS_HASWELL
    emit_lrm(&cmd_buffer->batch, CS_GPR(MI_ALU_REG14), count_address);
    emit_lri(&cmd_buffer->batch, CS_GPR(MI_ALU_REG14) + 4, 0);
+#endif
 
    for (uint32_t i = 0; i < maxDrawCount; i++) {
       struct anv_address draw = anv_address_add(buffer->address, offset);
@@ -3108,8 +3115,10 @@ void genX(CmdDrawIndexedIndirectCountKHR)(
      pc.PipeControlFlushEnable = true;
    }
 
+#if GEN_GEN >= 8 || GEN_IS_HASWELL
    emit_lrm(&cmd_buffer->batch, CS_GPR(MI_ALU_REG14), count_address);
    emit_lri(&cmd_buffer->batch, CS_GPR(MI_ALU_REG14) + 4, 0);
+#endif
 
    for (uint32_t i = 0; i < maxDrawCount; i++) {
       struct anv_address draw = anv_address_add(buffer->address, offset);
@@ -3135,7 +3144,6 @@ void genX(CmdDrawIndexedIndirectCountKHR)(
       offset += stride;
    }
 }
-#endif
 
 static VkResult
 flush_compute_descriptor_set(struct anv_cmd_buffer *cmd_buffer)
-- 
2.18.0