[Mesa-dev] [PATCH] i965/icl: Set Error Detection Behavior Control Bit in L3CNTLREG

[Lionel Landwerlin]

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>

On 25/10/2018 18:13, Anuj Phogat wrote:
> The default setting of this bit is not the desirable behavior.
> WA_1406697149
>
> Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
> ---
>   src/mesa/drivers/dri/i965/brw_defines.h      | 1 +
>   src/mesa/drivers/dri/i965/brw_state_upload.c | 7 +++++++
>   2 files changed, 8 insertions(+)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
> index 97a787a2ab3..897c91aa31e 100644
> --- a/src/mesa/drivers/dri/i965/brw_defines.h
> +++ b/src/mesa/drivers/dri/i965/brw_defines.h
> @@ -1646,6 +1646,7 @@ enum brw_pixel_shader_coverage_mask_mode {
>   # define GEN8_L3CNTLREG_DC_ALLOC_MASK      INTEL_MASK(24, 18)
>   # define GEN8_L3CNTLREG_ALL_ALLOC_SHIFT    25
>   # define GEN8_L3CNTLREG_ALL_ALLOC_MASK     INTEL_MASK(31, 25)
> +# define GEN8_L3CNTLREG_EDBC_NO_HANG       (1 << 9)
>   
>   #define GEN10_CACHE_MODE_SS            0x0e420
>   #define GEN10_FLOAT_BLEND_OPTIMIZATION_ENABLE (1 << 4)
> diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c
> index 7f20579fb87..60b72bf4ab3 100644
> --- a/src/mesa/drivers/dri/i965/brw_state_upload.c
> +++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
> @@ -79,6 +79,13 @@ brw_upload_initial_gpu_state(struct brw_context *brw)
>         brw_load_register_imm32(brw, HALF_SLICE_CHICKEN7,
>                                 TEXEL_OFFSET_FIX_MASK |
>                                 TEXEL_OFFSET_FIX_ENABLE);
> +
> +      /* WA_1406697149: Bit 9 "Error Detection Behavior Control" must be set
> +       * in L3CNTLREG register. The default setting of the bit is not the
> +       * desirable behavior.
> +       */
> +      brw_load_register_imm32(brw, GEN8_L3CNTLREG,
> +                              GEN8_L3CNTLREG_EDBC_NO_HANG);
>      }
>   
>      if (devinfo->gen == 10 || devinfo->gen == 11) {