[Mesa-dev] intel/icl: RFC: Two hardware workarounds

Topi Pohjolainen topi.pohjolainen at gmail.com
Mon Oct 29 12:38:56 UTC 2018


These don't seem to fix anything (hence RFC). Moreover, vertex
combining is not documented to harm anything. I thought better
having them in the list anyway.

CC: Anuj Phogat <anuj.phogat at gmail.com>

Topi Pohjolainen (2):
  intel/icl: Disable combining of vertices from separate instances
  intel/isl/icl: Use halign == 8 instead 4 hw workaround

 src/intel/blorp/blorp_genX_exec.h             |  6 ++++
 src/intel/isl/isl_gen8.c                      | 35 +++++++++++++++++++
 src/intel/vulkan/genX_pipeline.c              |  6 ++++
 src/mesa/drivers/dri/i965/genX_state_upload.c |  6 ++++
 4 files changed, 53 insertions(+)

-- 
2.17.1



More information about the mesa-dev mailing list