[Mesa-dev] [PATCH] i965/icl: Disable prefetching of sampler state entries

[Kenneth Graunke]

On Wednesday, October 24, 2018 11:33:53 AM PDT Anuj Phogat wrote:
> From: Topi Pohjolainen <topi.pohjolainen at intel.com>
> 
> In the same spirit as commit a5889d70f2074201ceaeac4f96a9a0c0b1f68a31
> "i965/icl: Disable binding table prefetching". Fixes some 110+
> intermittent piglit failures with tex-miplevel-selection variants.
> 
> WA_1606682166:
> Incorrect TDL's SSP address shift in SARB for 16:6 & 18:8 modes.
> Disable the Sampler state prefetch functionality in the SARB by
> programming 0xB000[30] to '1'. This is to be done at boot time and
> the feature must remain disabled permanently.
> 
> Anuj: Set SamplerCount = 0 for vs, gs, hs, ds and wm units as well.
> 
> Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
> Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
> Cc: Mark Janes <mark.a.janes at intel.com>
> ---
> Latest kernel from drm-tip  do have this workaround implemented
> but we're seeing few deqp regressions with that kernel. I'm
> adding this workaround to Mesa to make some progress in ICL
> testing on CI. We can always revert the patch when we don't
> need it anymore.
> ---
>  src/mesa/drivers/dri/i965/genX_state_upload.c | 15 ++++++++++++---
>  1 file changed, 12 insertions(+), 3 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c b/src/mesa/drivers/dri/i965/genX_state_upload.c
> index 740cb0c4d2e..319800934d5 100644
> --- a/src/mesa/drivers/dri/i965/genX_state_upload.c
> +++ b/src/mesa/drivers/dri/i965/genX_state_upload.c
> @@ -2004,7 +2004,8 @@ genX(upload_wm)(struct brw_context *brw)
>        if (wm_prog_data->base.use_alt_mode)
>           wm.FloatingPointMode = FLOATING_POINT_MODE_Alternate;
>  
> -      wm.SamplerCount = GEN_GEN == 5 ?
> +      /* WA_1606682166 */
> +      wm.SamplerCount = (GEN_GEN == 5 || GEN_GEN == 11) ?
>           0 : DIV_ROUND_UP(stage_state->sampler_count, 4);
>  
>        wm.BindingTableEntryCount =
> @@ -2166,7 +2167,10 @@ static const struct brw_tracked_state genX(wm_state) = {
>  
>  #define INIT_THREAD_DISPATCH_FIELDS(pkt, prefix) \
>     pkt.KernelStartPointer = KSP(brw, stage_state->prog_offset);           \
> +   /* WA_1606682166 */                                                    \
>     pkt.SamplerCount       =                                               \
> +      GEN_GEN == 11 ?                                                     \
> +      0 :                                                                 \

     pkt.SamplerCount       = GEN_GEN == 11 ? 0 :                           \

>        DIV_ROUND_UP(CLAMP(stage_state->sampler_count, 0, 16), 4);          \
>     /* Gen 11 workarounds table #2056 WABTPPrefetchDisable suggests to     \
>      * disable prefetching of binding tables in A0 and B0 steppings.       \
> @@ -3977,8 +3981,13 @@ genX(upload_ps)(struct brw_context *brw)
>         */
>        ps.VectorMaskEnable = GEN_GEN >= 8;
>  
> -      ps.SamplerCount =
> -         DIV_ROUND_UP(CLAMP(stage_state->sampler_count, 0, 16), 4);
> +   /* WA_1606682166:
> +    * "Incorrect TDL's SSP address shift in SARB for 16:6 & 18:8 modes.
> +    * Disable the Sampler state prefetch functionality in the SARB by
> +    * programming 0xB000[30] to '1'."
> +    */

Indentation

Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

> +      ps.SamplerCount = GEN_GEN == 11 ?
> +         0 : DIV_ROUND_UP(CLAMP(stage_state->sampler_count, 0, 16), 4);
>  
>        /* BRW_NEW_FS_PROG_DATA */
>        /* Gen 11 workarounds table #2056 WABTPPrefetchDisable suggests to disable
> 

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