[Mesa-dev] [PATCH 0/3] nir: Rework 64-bit attribute handling
Jason Ekstrand
jason at jlekstrand.net
Sat Sep 1 03:11:31 UTC 2018
NIR handling of 64-bit vertex attributes is inconsistent at best. When it
comes vertex attributes which are 196 or 256 bits (dvec3 or dvec4), some
passes assume they consume two slots, some passes assume they consume one,
and some passes are configurable. When you combine that with the limited
number of tests and apps which use attrib_64bit, it's an utter minefield.
Since both gallium and i965 want 196-bit and 256-bit attributes to map to
two slots eventually, you have the challenge of mapping back and forth
between the two in all the right places. This series attempts to fix the
problem and make all of NIR consistently have the dual-slot behavior.
Cc: Timothy Arceri <tarceri at itsqueeze.com>
Jason Ekstrand (3):
compiler: Move double_inputs to gl_program::DualSlotInputs
radeonsi/nir: Set vs_inputs_dual_locations and let NIR do the remap
nir: Drop the vs_inputs_dual_locations option
src/amd/vulkan/radv_shader.c | 1 -
src/compiler/glsl/glsl_to_nir.cpp | 11 +----
src/compiler/glsl/ir_set_program_inouts.cpp | 2 +-
src/compiler/glsl/serialize.cpp | 2 +
src/compiler/nir/nir.c | 45 ++++++++++++++-----
src/compiler/nir/nir.h | 11 ++---
src/compiler/nir/nir_gather_info.c | 26 ++---------
.../nir/nir_lower_io_arrays_to_elements.c | 5 +--
src/compiler/shader_info.h | 3 --
src/intel/compiler/brw_compiler.c | 3 --
src/mesa/drivers/dri/i965/brw_draw_upload.c | 21 ++++-----
src/mesa/drivers/dri/i965/genX_state_upload.c | 1 +
src/mesa/main/glspirv.c | 20 +--------
src/mesa/main/mtypes.h | 15 +++++++
src/mesa/state_tracker/st_glsl_to_nir.cpp | 45 +++++++++----------
src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 2 +-
src/mesa/state_tracker/st_program.c | 3 +-
17 files changed, 96 insertions(+), 120 deletions(-)
--
2.17.1
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