[Mesa-dev] [PATCH 0/8] Gallium & RadeonSI optimization for Ryzen CPUs

[Alan Swanson]

On Fri, 2018-09-07 at 15:01 -0400, Marek Olšák wrote:
> On Fri, Sep 7, 2018 at 11:04 AM, Michel Dänzer <michel at daenzer.net>
> wrote:
> > On 2018-09-07 4:31 p.m., Marek Olšák wrote:
> > > 
> > > I don't think the performance can be worse than it is right now.
> > 
> > In the worst case, all processes using OpenGL (or at least their
> > OpenGL
> > related threads, but that usually includes the main thread) could
> > end up
> > restricted to the same 4 cores, leaving up to 28 cores underused.
> 
> 4C/4T used to be a standard and certainly enough for gaming. 4C/8T
> used to be luxury before Ryzen, which is now the CCX. We should be
> fine with 4 cores.

So, for Ryzen processors where the CCX core split is 2+2 (1400/1500) or
3+3 (1600/2600) would you not be potentially overloading each CCX
(regardless of SMT)?

Otherwise, isn't a significant issue the CCX interconnect being
hamstrung by being linked to memory speed and if you have fast memory
(2933+) it's not such a burden?

-- 
Alan.