[Mesa-dev] [PATCH 05/11] i965/fs: Eliminate dead code first
Ian Romanick
idr at freedesktop.org
Mon Sep 10 23:29:08 UTC 2018
From: Ian Romanick <ian.d.romanick at intel.com>
This simplifies the later patch "i965/fs: Generate better code for fsign
multiplied by a value".
shader-db results:
Broadwell and Skylake had similar results. (Skylake shown)
total cycles in shared programs: 566050075 -> 566053975 (<.01%)
cycles in affected programs: 1342167 -> 1346067 (0.29%)
helped: 231
HURT: 266
helped stats (abs) min: 1 max: 204 x̄: 13.30 x̃: 4
helped stats (rel) min: 0.01% max: 5.61% x̄: 0.45% x̃: 0.21%
HURT stats (abs) min: 1 max: 623 x̄: 26.21 x̃: 5
HURT stats (rel) min: 0.02% max: 15.20% x̄: 1.00% x̃: 0.28%
95% mean confidence interval for cycles value: 3.34 12.35
95% mean confidence interval for cycles %-change: 0.18% 0.47%
Cycles are HURT.
Sandy Bridge, Ivy Bridge, and Haswell had similar results. (Haswell shown)
total cycles in shared programs: 449617838 -> 449616551 (<.01%)
cycles in affected programs: 419356 -> 418069 (-0.31%)
helped: 44
HURT: 44
helped stats (abs) min: 1 max: 317 x̄: 86.75 x̃: 54
helped stats (rel) min: 0.03% max: 6.53% x̄: 1.56% x̃: 1.01%
HURT stats (abs) min: 2 max: 221 x̄: 57.50 x̃: 19
HURT stats (rel) min: 0.03% max: 9.46% x̄: 1.77% x̃: 0.54%
95% mean confidence interval for cycles value: -37.19 7.94
95% mean confidence interval for cycles %-change: -0.46% 0.67%
Inconclusive result (value mean confidence interval includes 0).
GM45 and Iron Lake had similar results. (Iron Lake shown)
total cycles in shared programs: 187478814 -> 187478820 (<.01%)
cycles in affected programs: 102438 -> 102444 (<.01%)
helped: 2
HURT: 3
helped stats (abs) min: 2 max: 4 x̄: 3.00 x̃: 3
helped stats (rel) min: <.01% max: 0.03% x̄: 0.02% x̃: 0.02%
HURT stats (abs) min: 4 max: 4 x̄: 4.00 x̃: 4
HURT stats (rel) min: 0.03% max: 0.03% x̄: 0.03% x̃: 0.03%
95% mean confidence interval for cycles value: -3.64 6.04
95% mean confidence interval for cycles %-change: -0.02% 0.04%
Inconclusive result (value mean confidence interval includes 0).
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
---
src/intel/compiler/brw_fs.cpp | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index f19fa783a96..722c36a4e20 100644
--- a/src/intel/compiler/brw_fs.cpp
+++ b/src/intel/compiler/brw_fs.cpp
@@ -6299,6 +6299,14 @@ fs_visitor::optimize()
int iteration = 0;
int pass_num = 0;
+ /* Before anything else, eliminate dead code. The results of some NIR
+ * instructions may effectively be calculated twice. Once when the
+ * instruction is encountered, and again when the user of that result is
+ * encountered. Wipe those away before algebraic optimizations and
+ * especially copy propagation can mix things up.
+ */
+ OPT(dead_code_eliminate);
+
OPT(remove_extra_rounding_modes);
do {
--
2.14.4
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