[Mesa-dev] [PATCH 3/6] radeonsi:optimizing SET_CONTEXT_REG for shaders VS
Sonny Jiang
sonny.jiang at amd.com
Tue Sep 18 20:21:12 UTC 2018
Signed-off-by: Sonny Jiang <sonny.jiang at amd.com>
---
src/gallium/drivers/radeonsi/si_gfx_cs.c | 6 +
src/gallium/drivers/radeonsi/si_state.h | 6 +
.../drivers/radeonsi/si_state_shaders.c | 133 +++++++++++-------
3 files changed, 93 insertions(+), 52 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_gfx_cs.c b/src/gallium/drivers/radeonsi/si_gfx_cs.c
index 39a97bf3da..2e10d766a6 100644
--- a/src/gallium/drivers/radeonsi/si_gfx_cs.c
+++ b/src/gallium/drivers/radeonsi/si_gfx_cs.c
@@ -365,6 +365,12 @@ void si_begin_new_gfx_cs(struct si_context *ctx)
ctx->tracked_regs.reg_value[SI_TRACKED_VGT_GS_INSTANCE_CNT] = 0x00000000;
ctx->tracked_regs.reg_value[SI_TRACKED_VGT_GS_ONCHIP_CNTL] = 0x00000000;
ctx->tracked_regs.reg_value[SI_TRACKED_VGT_GS_MAX_PRIMS_PER_SUBGROUP] = 0x00000000;
+ ctx->tracked_regs.reg_value[SI_TRACKED_VGT_GS_MODE] = 0x00000000;
+ ctx->tracked_regs.reg_value[SI_TRACKED_VGT_PRIMITIVEID_EN] = 0x00000000;
+ ctx->tracked_regs.reg_value[SI_TRACKED_VGT_REUSE_OFF] = 0x00000000;
+ ctx->tracked_regs.reg_value[SI_TRACKED_SPI_VS_OUT_CONFIG] = 0x00000000;
+ ctx->tracked_regs.reg_value[SI_TRACKED_SPI_SHADER_POS_FORMAT] = 0x00000000;
+ ctx->tracked_regs.reg_value[SI_TRACKED_PA_CL_VTE_CNTL] = 0x00000000;
/* Set all saved registers state to saved. */
ctx->tracked_regs.reg_saved = 0xffffffffffffffff;
diff --git a/src/gallium/drivers/radeonsi/si_state.h b/src/gallium/drivers/radeonsi/si_state.h
index 9efb4be5a5..bf1ae9f18f 100644
--- a/src/gallium/drivers/radeonsi/si_state.h
+++ b/src/gallium/drivers/radeonsi/si_state.h
@@ -295,6 +295,12 @@ enum si_tracked_reg {
SI_TRACKED_VGT_GS_INSTANCE_CNT,
SI_TRACKED_VGT_GS_ONCHIP_CNTL,
SI_TRACKED_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
+ SI_TRACKED_VGT_GS_MODE,
+ SI_TRACKED_VGT_PRIMITIVEID_EN,
+ SI_TRACKED_VGT_REUSE_OFF,
+ SI_TRACKED_SPI_VS_OUT_CONFIG,
+ SI_TRACKED_SPI_SHADER_POS_FORMAT,
+ SI_TRACKED_PA_CL_VTE_CNTL,
SI_NUM_TRACKED_REGS,
};
diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c b/src/gallium/drivers/radeonsi/si_state_shaders.c
index 87b58cd6e5..332fdae3b3 100644
--- a/src/gallium/drivers/radeonsi/si_state_shaders.c
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
@@ -914,29 +914,23 @@ static void si_shader_gs(struct si_screen *sscreen, struct si_shader *shader)
}
}
-/**
- * Compute the state for \p shader, which will run as a vertex shader on the
- * hardware.
- *
- * If \p gs is non-NULL, it points to the geometry shader for which this shader
- * is the copy shader.
- */
-static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader,
- struct si_shader_selector *gs)
+static void si_emit_shader_vs(struct si_context *sctx)
{
+ struct si_shader *shader = sctx->queued.named.vs->shader;
+ if (!shader)
+ return;
+
+ struct si_shader_selector *gs;
const struct tgsi_shader_info *info = &shader->selector->info;
- struct si_pm4_state *pm4;
- unsigned num_user_sgprs;
- unsigned nparams, vgpr_comp_cnt;
- uint64_t va;
- unsigned oc_lds_en;
+ unsigned nparams;
unsigned window_space =
info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
bool enable_prim_id = shader->key.mono.u.vs_export_prim_id || info->uses_primid;
- pm4 = si_get_shader_pm4_state(shader);
- if (!pm4)
- return;
+ if (shader->is_gs_copy_shader)
+ gs = shader->selector;
+ else
+ gs = NULL;
/* We always write VGT_GS_MODE in the VS state, because every switch
* between different shader pipelines involving a different GS or no
@@ -952,21 +946,82 @@ static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader,
if (enable_prim_id)
mode = V_028A40_GS_SCENARIO_A;
- si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, S_028A40_MODE(mode));
- si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, enable_prim_id);
+ radeon_opt_set_context_reg(sctx, R_028A40_VGT_GS_MODE,
+ SI_TRACKED_VGT_GS_MODE,
+ S_028A40_MODE(mode));
+ radeon_opt_set_context_reg(sctx, R_028A84_VGT_PRIMITIVEID_EN,
+ SI_TRACKED_VGT_PRIMITIVEID_EN,
+ enable_prim_id);
} else {
- si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE,
- ac_vgt_gs_mode(gs->gs_max_out_vertices,
- sscreen->info.chip_class));
- si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0);
+ radeon_opt_set_context_reg(sctx, R_028A40_VGT_GS_MODE,
+ SI_TRACKED_VGT_GS_MODE,
+ ac_vgt_gs_mode(gs->gs_max_out_vertices,
+ sctx->chip_class));
+ radeon_opt_set_context_reg(sctx, R_028A84_VGT_PRIMITIVEID_EN,
+ SI_TRACKED_VGT_PRIMITIVEID_EN, 0);
}
- if (sscreen->info.chip_class <= VI) {
+ if (sctx->chip_class <= VI) {
/* Reuse needs to be set off if we write oViewport. */
- si_pm4_set_reg(pm4, R_028AB4_VGT_REUSE_OFF,
- S_028AB4_REUSE_OFF(info->writes_viewport_index));
+ radeon_opt_set_context_reg(sctx, R_028AB4_VGT_REUSE_OFF,
+ SI_TRACKED_VGT_REUSE_OFF,
+ S_028AB4_REUSE_OFF(info->writes_viewport_index));
}
+ /* VS is required to export at least one param. */
+ nparams = MAX2(shader->info.nr_param_exports, 1);
+ radeon_opt_set_context_reg(sctx, R_0286C4_SPI_VS_OUT_CONFIG,
+ SI_TRACKED_SPI_VS_OUT_CONFIG,
+ S_0286C4_VS_EXPORT_COUNT(nparams - 1));
+
+ radeon_opt_set_context_reg(sctx, R_02870C_SPI_SHADER_POS_FORMAT,
+ SI_TRACKED_SPI_SHADER_POS_FORMAT,
+ S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
+ S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
+ V_02870C_SPI_SHADER_4COMP :
+ V_02870C_SPI_SHADER_NONE) |
+ S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
+ V_02870C_SPI_SHADER_4COMP :
+ V_02870C_SPI_SHADER_NONE) |
+ S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
+ V_02870C_SPI_SHADER_4COMP :
+ V_02870C_SPI_SHADER_NONE));
+
+ if (window_space)
+ radeon_opt_set_context_reg(sctx, R_028818_PA_CL_VTE_CNTL,
+ SI_TRACKED_PA_CL_VTE_CNTL,
+ S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
+ else
+ radeon_opt_set_context_reg(sctx, R_028818_PA_CL_VTE_CNTL,
+ SI_TRACKED_PA_CL_VTE_CNTL,
+ S_028818_VTX_W0_FMT(1) |
+ S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
+ S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
+ S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
+}
+
+/**
+ * Compute the state for \p shader, which will run as a vertex shader on the
+ * hardware.
+ *
+ * If \p gs is non-NULL, it points to the geometry shader for which this shader
+ * is the copy shader.
+ */
+static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader,
+ struct si_shader_selector *gs)
+{
+ const struct tgsi_shader_info *info = &shader->selector->info;
+ struct si_pm4_state *pm4;
+ unsigned num_user_sgprs, vgpr_comp_cnt;
+ uint64_t va;
+ unsigned oc_lds_en;
+ bool enable_prim_id = shader->key.mono.u.vs_export_prim_id || info->uses_primid;
+
+ pm4 = si_get_shader_pm4_state(shader);
+ if (!pm4)
+ return;
+
+ pm4->atom.emit = si_emit_shader_vs;
va = shader->bo->gpu_address;
si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
@@ -992,23 +1047,6 @@ static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader,
} else
unreachable("invalid shader selector type");
- /* VS is required to export at least one param. */
- nparams = MAX2(shader->info.nr_param_exports, 1);
- si_pm4_set_reg(pm4, R_0286C4_SPI_VS_OUT_CONFIG,
- S_0286C4_VS_EXPORT_COUNT(nparams - 1));
-
- si_pm4_set_reg(pm4, R_02870C_SPI_SHADER_POS_FORMAT,
- S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
- S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
- V_02870C_SPI_SHADER_4COMP :
- V_02870C_SPI_SHADER_NONE) |
- S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
- V_02870C_SPI_SHADER_4COMP :
- V_02870C_SPI_SHADER_NONE) |
- S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
- V_02870C_SPI_SHADER_4COMP :
- V_02870C_SPI_SHADER_NONE));
-
oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
@@ -1028,15 +1066,6 @@ static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader,
S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
S_00B12C_SO_EN(!!shader->selector->so.num_outputs) |
S_00B12C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
- if (window_space)
- si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
- S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
- else
- si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
- S_028818_VTX_W0_FMT(1) |
- S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
- S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
- S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
si_set_tesseval_regs(sscreen, shader->selector, pm4);
--
2.17.1
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