[Mesa-dev] [PATCH 4/5] radeonsi: don't set the VS prolog key for the blit VS

[Marek Olšák]

From: Marek Olšák <marek.olsak at amd.com>

---
 src/gallium/drivers/radeonsi/si_state_shaders.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c b/src/gallium/drivers/radeonsi/si_state_shaders.c
index 157a0e3..0bf783f 100644
--- a/src/gallium/drivers/radeonsi/si_state_shaders.c
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
@@ -1187,21 +1187,22 @@ static unsigned si_get_alpha_test_func(struct si_context *sctx)
 		return sctx->queued.named.dsa->alpha_func;
 
 	return PIPE_FUNC_ALWAYS;
 }
 
 static void si_shader_selector_key_vs(struct si_context *sctx,
 				      struct si_shader_selector *vs,
 				      struct si_shader_key *key,
 				      struct si_vs_prolog_bits *prolog_key)
 {
-	if (!sctx->vertex_elements)
+	if (!sctx->vertex_elements ||
+	    vs->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS])
 		return;
 
 	prolog_key->instance_divisor_is_one =
 		sctx->vertex_elements->instance_divisor_is_one;
 	prolog_key->instance_divisor_is_fetched =
 		sctx->vertex_elements->instance_divisor_is_fetched;
 
 	/* Prefer a monolithic shader to allow scheduling divisions around
 	 * VBO loads. */
 	if (prolog_key->instance_divisor_is_fetched)
-- 
2.7.4