[Mesa-dev] [PATCH 08/20] intel/aub_write: turn context images arrays into functions
Lionel Landwerlin
lionel.g.landwerlin at intel.com
Tue Sep 25 08:23:47 UTC 2018
We'll make them more parameterized in a later commit.
As this is just a transitional commit, we allow ourself to leak the
context images allocated in get_context_init(). We'll fix this in the
next commit.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
---
src/intel/tools/aub_write.c | 62 ++++----
src/intel/tools/gen10_context.h | 250 +++++++++++++++++---------------
src/intel/tools/gen8_context.h | 228 ++++++++++++++++-------------
src/intel/tools/gen_context.h | 8 +
4 files changed, 306 insertions(+), 242 deletions(-)
diff --git a/src/intel/tools/aub_write.c b/src/intel/tools/aub_write.c
index 6c584a4dfc3..b51a1069d96 100644
--- a/src/intel/tools/aub_write.c
+++ b/src/intel/tools/aub_write.c
@@ -56,28 +56,6 @@ mem_trace_memory_write_header_out(struct aub_file *aub, uint64_t addr,
uint32_t len, uint32_t addr_space,
const char *desc);
-static const uint32_t *
-get_context_init(const struct gen_device_info *devinfo,
- enum drm_i915_gem_engine_class engine_class)
-{
- static const uint32_t *gen8_contexts[] = {
- [I915_ENGINE_CLASS_RENDER] = gen8_render_context_init,
- [I915_ENGINE_CLASS_COPY] = gen8_blitter_context_init,
- [I915_ENGINE_CLASS_VIDEO] = gen8_video_context_init,
- };
- static const uint32_t *gen10_contexts[] = {
- [I915_ENGINE_CLASS_RENDER] = gen10_render_context_init,
- [I915_ENGINE_CLASS_COPY] = gen10_blitter_context_init,
- [I915_ENGINE_CLASS_VIDEO] = gen10_video_context_init,
- };
-
- assert(devinfo->gen >= 8);
-
- if (devinfo->gen <= 10)
- return gen8_contexts[engine_class];
- return gen10_contexts[engine_class];
-}
-
static void __attribute__ ((format(__printf__, 2, 3)))
fail_if(int cond, const char *format, ...)
{
@@ -377,6 +355,36 @@ ppgtt_lookup(struct aub_file *aub, uint64_t ppgtt_addr)
return (uint64_t)L1_table(ppgtt_addr)->subtables[L1_index(ppgtt_addr)];
}
+static uint32_t *
+get_context_init(const struct gen_device_info *devinfo,
+ enum drm_i915_gem_engine_class engine_class,
+ uint32_t *size)
+{
+ static void (* const gen8_contexts[])(uint32_t *, uint32_t *) = {
+ [I915_ENGINE_CLASS_RENDER] = gen8_render_context_init,
+ [I915_ENGINE_CLASS_COPY] = gen8_blitter_context_init,
+ [I915_ENGINE_CLASS_VIDEO] = gen8_video_context_init,
+ };
+ static void (* const gen10_contexts[])(uint32_t *, uint32_t *) = {
+ [I915_ENGINE_CLASS_RENDER] = gen10_render_context_init,
+ [I915_ENGINE_CLASS_COPY] = gen10_blitter_context_init,
+ [I915_ENGINE_CLASS_VIDEO] = gen10_video_context_init,
+ };
+
+ assert(devinfo->gen >= 8);
+
+ void (*func)(uint32_t *, uint32_t *);
+ if (devinfo->gen <= 10)
+ func = gen8_contexts[engine_class];
+ else
+ func = gen10_contexts[engine_class];
+
+ func(NULL, size);
+ uint32_t *data = calloc(*size / sizeof(uint32_t), sizeof(uint32_t));
+ func(data, size);
+ return data;
+}
+
static void
write_execlists_default_setup(struct aub_file *aub)
{
@@ -385,6 +393,7 @@ write_execlists_default_setup(struct aub_file *aub)
*/
uint32_t ggtt_ptes = STATIC_GGTT_MAP_SIZE >> 12;
uint64_t phys_addr = aub->phys_addrs_allocator << 12;
+ uint32_t context_size;
aub->phys_addrs_allocator += ggtt_ptes;
@@ -416,7 +425,8 @@ write_execlists_default_setup(struct aub_file *aub)
dword_out(aub, 0);
/* RENDER_CONTEXT */
- data_out(aub, get_context_init(&aub->devinfo, I915_ENGINE_CLASS_RENDER), CONTEXT_RENDER_SIZE);
+ data_out(aub, get_context_init(&aub->devinfo, I915_ENGINE_CLASS_RENDER, &context_size), CONTEXT_RENDER_SIZE);
+ assert(context_size == CONTEXT_RENDER_SIZE);
/* BLITTER_RING */
mem_trace_memory_write_header_out(aub, phys_addr + BLITTER_RING_ADDR, RING_SIZE,
@@ -435,7 +445,8 @@ write_execlists_default_setup(struct aub_file *aub)
dword_out(aub, 0);
/* BLITTER_CONTEXT */
- data_out(aub, get_context_init(&aub->devinfo, I915_ENGINE_CLASS_COPY), CONTEXT_OTHER_SIZE);
+ data_out(aub, get_context_init(&aub->devinfo, I915_ENGINE_CLASS_COPY, &context_size), CONTEXT_OTHER_SIZE);
+ assert(context_size == CONTEXT_OTHER_SIZE);
/* VIDEO_RING */
mem_trace_memory_write_header_out(aub, phys_addr + VIDEO_RING_ADDR, RING_SIZE,
@@ -454,7 +465,8 @@ write_execlists_default_setup(struct aub_file *aub)
dword_out(aub, 0);
/* VIDEO_CONTEXT */
- data_out(aub, get_context_init(&aub->devinfo, I915_ENGINE_CLASS_VIDEO), CONTEXT_OTHER_SIZE);
+ data_out(aub, get_context_init(&aub->devinfo, I915_ENGINE_CLASS_VIDEO, &context_size), CONTEXT_OTHER_SIZE);
+ assert(context_size == CONTEXT_OTHER_SIZE);
register_write_out(aub, HWS_PGA_RCSUNIT, RENDER_CONTEXT_ADDR);
register_write_out(aub, HWS_PGA_VCSUNIT0, VIDEO_CONTEXT_ADDR);
diff --git a/src/intel/tools/gen10_context.h b/src/intel/tools/gen10_context.h
index 8b1973c513c..a6e6c340fc6 100644
--- a/src/intel/tools/gen10_context.h
+++ b/src/intel/tools/gen10_context.h
@@ -24,118 +24,142 @@
#ifndef GEN10_CONTEXT_H
#define GEN10_CONTEXT_H
-static const uint32_t gen10_render_context_init[CONTEXT_RENDER_SIZE / sizeof(uint32_t)] = {
- 0 /* MI_NOOP */,
- MI_LOAD_REGISTER_IMM_n(14) | MI_LRI_FORCE_POSTED,
- 0x2244 /* CONTEXT_CONTROL */, 0x90009 /* Inhibit Synchronous Context Switch | Engine Context Restore Inhibit */,
- 0x2034 /* RING_HEAD */, 0,
- 0x2030 /* RING_TAIL */, 0,
- 0x2038 /* RING_BUFFER_START */, RENDER_RING_ADDR,
- 0x203C /* RING_BUFFER_CONTROL */, (RING_SIZE - 4096) | 1 /* Buffer Length | Ring Buffer Enable */,
- 0x2168 /* BB_HEAD_U */, 0,
- 0x2140 /* BB_HEAD_L */, 0,
- 0x2110 /* BB_STATE */, 0,
- 0x211C /* SECOND_BB_HEAD_U */, 0,
- 0x2114 /* SECOND_BB_HEAD_L */, 0,
- 0x2118 /* SECOND_BB_STATE */, 0,
- 0x21C0 /* BB_PER_CTX_PTR */, 0,
- 0x21C4 /* RCS_INDIRECT_CTX */, 0,
- 0x21C8 /* RCS_INDIRECT_CTX_OFFSET */, 0,
- 0x2180 /* CCID */, 0,
-
- 0 /* MI_NOOP */,
- MI_LOAD_REGISTER_IMM_n(9) | MI_LRI_FORCE_POSTED,
- 0x23A8 /* CTX_TIMESTAMP */, 0,
- 0x228C /* PDP3_UDW */, 0,
- 0x2288 /* PDP3_LDW */, 0,
- 0x2284 /* PDP2_UDW */, 0,
- 0x2280 /* PDP2_LDW */, 0,
- 0x227C /* PDP1_UDW */, 0,
- 0x2278 /* PDP1_LDW */, 0,
- 0x2274 /* PDP0_UDW */, PML4_PHYS_ADDR >> 32,
- 0x2270 /* PDP0_LDW */, PML4_PHYS_ADDR,
- /* MI_NOOP */
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-
- 0 /* MI_NOOP */,
- MI_LOAD_REGISTER_IMM_n(1),
- 0x20C8 /* R_PWR_CLK_STATE */, 0x7FFFFFFF,
- 0, 0, 0 /* GPGPU_CSR_BASE_ADDRESS ? */,
- 0, 0, 0, 0, 0, 0, 0, 0, 0 /* MI_NOOP */,
-
- MI_BATCH_BUFFER_END | 1 /* End Context */
-};
-
-static const uint32_t gen10_blitter_context_init[CONTEXT_OTHER_SIZE / sizeof(uint32_t)] = {
- 0 /* MI_NOOP */,
- MI_LOAD_REGISTER_IMM_n(14) | MI_LRI_FORCE_POSTED,
- 0x22244 /* CONTEXT_CONTROL */, 0x90009 /* Inhibit Synchronous Context Switch | Engine Context Restore Inhibit */,
- 0x22034 /* RING_HEAD */, 0,
- 0x22030 /* RING_TAIL */, 0,
- 0x22038 /* RING_BUFFER_START */, BLITTER_RING_ADDR,
- 0x2203C /* RING_BUFFER_CONTROL */, (RING_SIZE - 4096) | 1 /* Buffer Length | Ring Buffer Enable */,
- 0x22168 /* BB_HEAD_U */, 0,
- 0x22140 /* BB_HEAD_L */, 0,
- 0x22110 /* BB_STATE */, 0,
- 0x2211C /* SECOND_BB_HEAD_U */, 0,
- 0x22114 /* SECOND_BB_HEAD_L */, 0,
- 0x22118 /* SECOND_BB_STATE */, 0,
- 0x221C0 /* BB_PER_CTX_PTR */, 0,
- 0x221C4 /* INDIRECT_CTX */, 0,
- 0x221C8 /* INDIRECT_CTX_OFFSET */, 0,
- 0, 0 /* MI_NOOP */,
-
- 0 /* MI_NOOP */,
- MI_LOAD_REGISTER_IMM_n(9) | MI_LRI_FORCE_POSTED,
- 0x223A8 /* CTX_TIMESTAMP */, 0,
- 0x2228C /* PDP3_UDW */, 0,
- 0x22288 /* PDP3_LDW */, 0,
- 0x22284 /* PDP2_UDW */, 0,
- 0x22280 /* PDP2_LDW */, 0,
- 0x2227C /* PDP1_UDW */, 0,
- 0x22278 /* PDP1_LDW */, 0,
- 0x22274 /* PDP0_UDW */, PML4_PHYS_ADDR >> 32,
- 0x22270 /* PDP0_LDW */, PML4_PHYS_ADDR,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 /* MI_NOOP */,
- MI_LOAD_REGISTER_IMM_n(1),
- 0x22200 /* BCS_SWCTRL */, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 /* MI_NOOP */,
-
- MI_BATCH_BUFFER_END | 1 /* End Context */
-};
-
-static const uint32_t gen10_video_context_init[CONTEXT_OTHER_SIZE / sizeof(uint32_t)] = {
- 0 /* MI_NOOP */,
- MI_LOAD_REGISTER_IMM_n(11) | MI_LRI_FORCE_POSTED,
- 0x1C244 /* CONTEXT_CONTROL */, 0x90009 /* Inhibit Synchronous Context Switch | Engine Context Restore Inhibit */,
- 0x1C034 /* RING_HEAD */, 0,
- 0x1C030 /* RING_TAIL */, 0,
- 0x1C038 /* RING_BUFFER_START */, VIDEO_RING_ADDR,
- 0x1C03C /* RING_BUFFER_CONTROL */, (RING_SIZE - 4096) | 1 /* Buffer Length | Ring Buffer Enable */,
- 0x1C168 /* BB_HEAD_U */, 0,
- 0x1C140 /* BB_HEAD_L */, 0,
- 0x1C110 /* BB_STATE */, 0,
- 0x1C11C /* SECOND_BB_HEAD_U */, 0,
- 0x1C114 /* SECOND_BB_HEAD_L */, 0,
- 0x1C118 /* SECOND_BB_STATE */, 0,
- /* MI_NOOP */
- 0, 0, 0, 0, 0, 0, 0, 0,
-
- 0 /* MI_NOOP */,
- MI_LOAD_REGISTER_IMM_n(9) | MI_LRI_FORCE_POSTED,
- 0x1C3A8 /* CTX_TIMESTAMP */, 0,
- 0x1C28C /* PDP3_UDW */, 0,
- 0x1C288 /* PDP3_LDW */, 0,
- 0x1C284 /* PDP2_UDW */, 0,
- 0x1C280 /* PDP2_LDW */, 0,
- 0x1C27C /* PDP1_UDW */, 0,
- 0x1C278 /* PDP1_LDW */, 0,
- 0x1C274 /* PDP0_UDW */, PML4_PHYS_ADDR >> 32,
- 0x1C270 /* PDP0_LDW */, PML4_PHYS_ADDR,
- /* MI_NOOP */
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-
- MI_BATCH_BUFFER_END | 1 /* End Context */
-};
+static inline void gen10_render_context_init(uint32_t *data, uint32_t *size)
+{
+ *size = CONTEXT_RENDER_SIZE;
+ if (!data)
+ return;
+
+ *data++ = 0; /* MI_NOOP */
+ MI_LOAD_REGISTER_IMM_vals(data, MI_LRI_FORCE_POSTED,
+ 0x2244 /* CONTEXT_CONTROL */, 0x90009 /* Inhibit Synchronous Context Switch | Engine Context Restore Inhibit */,
+ 0x2034 /* RING_HEAD */, 0,
+ 0x2030 /* RING_TAIL */, 0,
+ 0x2038 /* RING_BUFFER_START */, RENDER_RING_ADDR,
+ 0x203C /* RING_BUFFER_CONTROL */, (RING_SIZE - 4096) | 1 /* Buffer Length | Ring Buffer Enable */,
+ 0x2168 /* BB_HEAD_U */, 0,
+ 0x2140 /* BB_HEAD_L */, 0,
+ 0x2110 /* BB_STATE */, 0,
+ 0x211C /* SECOND_BB_HEAD_U */, 0,
+ 0x2114 /* SECOND_BB_HEAD_L */, 0,
+ 0x2118 /* SECOND_BB_STATE */, 0,
+ 0x21C0 /* BB_PER_CTX_PTR */, 0,
+ 0x21C4 /* RCS_INDIRECT_CTX */, 0,
+ 0x21C8 /* RCS_INDIRECT_CTX_OFFSET */, 0,
+ 0x2180 /* CCID */, 0);
+ *data++ = 0; /* MI_NOOP */
+
+ MI_LOAD_REGISTER_IMM_vals(data, MI_LRI_FORCE_POSTED,
+ 0x23A8 /* CTX_TIMESTAMP */, 0,
+ 0x228C /* PDP3_UDW */, 0,
+ 0x2288 /* PDP3_LDW */, 0,
+ 0x2284 /* PDP2_UDW */, 0,
+ 0x2280 /* PDP2_LDW */, 0,
+ 0x227C /* PDP1_UDW */, 0,
+ 0x2278 /* PDP1_LDW */, 0,
+ 0x2274 /* PDP0_UDW */, PML4_PHYS_ADDR >> 32,
+ 0x2270 /* PDP0_LDW */, PML4_PHYS_ADDR);
+ for (int i = 0; i < 12; i++)
+ *data++ = 0; /* MI_NOOP */
+
+ *data++ = 0; /* MI_NOOP */
+ MI_LOAD_REGISTER_IMM_vals(data, 0,
+ 0x20C8 /* R_PWR_CLK_STATE */, 0x7FFFFFFF,
+ 0, /* GPGPU_CSR_BASE_ADDRESS ? */ 0);
+ *data++ = 0; /* MI_NOOP */
+
+ for (int i = 0; i < 9; i++)
+ *data++ = 0;
+
+ *data++ = MI_BATCH_BUFFER_END | 1 /* End Context */;
+}
+
+static inline void gen10_blitter_context_init(uint32_t *data, uint32_t *size)
+{
+ *size = CONTEXT_OTHER_SIZE;
+ if (!data)
+ return;
+
+ *data++ = 0 /* MI_NOOP */;
+ MI_LOAD_REGISTER_IMM_vals(data, MI_LRI_FORCE_POSTED,
+ 0x22244 /* CONTEXT_CONTROL */, 0x90009 /* Inhibit Synchronous Context Switch | Engine Context Restore Inhibit */,
+ 0x22034 /* RING_HEAD */, 0,
+ 0x22030 /* RING_TAIL */, 0,
+ 0x22038 /* RING_BUFFER_START */, BLITTER_RING_ADDR,
+ 0x2203C /* RING_BUFFER_CONTROL */, (RING_SIZE - 4096) | 1 /* Buffer Length | Ring Buffer Enable */,
+ 0x22168 /* BB_HEAD_U */, 0,
+ 0x22140 /* BB_HEAD_L */, 0,
+ 0x22110 /* BB_STATE */, 0,
+ 0x2211C /* SECOND_BB_HEAD_U */, 0,
+ 0x22114 /* SECOND_BB_HEAD_L */, 0,
+ 0x22118 /* SECOND_BB_STATE */, 0,
+ 0x221C0 /* BB_PER_CTX_PTR */, 0,
+ 0x221C4 /* INDIRECT_CTX */, 0,
+ 0x221C8 /* INDIRECT_CTX_OFFSET */, 0);
+ *data++ = 0 /* MI_NOOP */;
+ *data++ = 0 /* MI_NOOP */;
+
+ *data++ = 0 /* MI_NOOP */;
+ MI_LOAD_REGISTER_IMM_vals(data, MI_LRI_FORCE_POSTED,
+ 0x223A8 /* CTX_TIMESTAMP */, 0,
+ 0x2228C /* PDP3_UDW */, 0,
+ 0x22288 /* PDP3_LDW */, 0,
+ 0x22284 /* PDP2_UDW */, 0,
+ 0x22280 /* PDP2_LDW */, 0,
+ 0x2227C /* PDP1_UDW */, 0,
+ 0x22278 /* PDP1_LDW */, 0,
+ 0x22274 /* PDP0_UDW */, PML4_PHYS_ADDR >> 32,
+ 0x22270 /* PDP0_LDW */, PML4_PHYS_ADDR);
+ for (int i = 0; i < 13; i++)
+ *data++ = 0 /* MI_NOOP */;
+
+ MI_LOAD_REGISTER_IMM_vals(data, 0,
+ 0x22200 /* BCS_SWCTRL */, 0);
+
+ for (int i = 0; i < 12; i++)
+ *data++ = 0 /* MI_NOOP */;
+
+
+ *data++ = MI_BATCH_BUFFER_END | 1 /* End Context */;
+}
+
+static inline void gen10_video_context_init(uint32_t *data, uint32_t *size)
+{
+ *size = CONTEXT_OTHER_SIZE;
+ if (!data)
+ return;
+
+ *data++ = 0 /* MI_NOOP */;
+ MI_LOAD_REGISTER_IMM_vals(data, MI_LRI_FORCE_POSTED,
+ 0x1C244 /* CONTEXT_CONTROL */, 0x90009 /* Inhibit Synchronous Context Switch | Engine Context Restore Inhibit */,
+ 0x1C034 /* RING_HEAD */, 0,
+ 0x1C030 /* RING_TAIL */, 0,
+ 0x1C038 /* RING_BUFFER_START */, VIDEO_RING_ADDR,
+ 0x1C03C /* RING_BUFFER_CONTROL */, (RING_SIZE - 4096) | 1 /* Buffer Length | Ring Buffer Enable */,
+ 0x1C168 /* BB_HEAD_U */, 0,
+ 0x1C140 /* BB_HEAD_L */, 0,
+ 0x1C110 /* BB_STATE */, 0,
+ 0x1C11C /* SECOND_BB_HEAD_U */, 0,
+ 0x1C114 /* SECOND_BB_HEAD_L */, 0,
+ 0x1C118 /* SECOND_BB_STATE */, 0);
+ for (int i = 0; i < 8; i++)
+ *data++ = 0 /* MI_NOOP */;
+
+ *data++ = 0 /* MI_NOOP */;
+ MI_LOAD_REGISTER_IMM_vals(data, MI_LRI_FORCE_POSTED,
+ 0x1C3A8 /* CTX_TIMESTAMP */, 0,
+ 0x1C28C /* PDP3_UDW */, 0,
+ 0x1C288 /* PDP3_LDW */, 0,
+ 0x1C284 /* PDP2_UDW */, 0,
+ 0x1C280 /* PDP2_LDW */, 0,
+ 0x1C27C /* PDP1_UDW */, 0,
+ 0x1C278 /* PDP1_LDW */, 0,
+ 0x1C274 /* PDP0_UDW */, PML4_PHYS_ADDR >> 32,
+ 0x1C270 /* PDP0_LDW */, PML4_PHYS_ADDR);
+ for (int i = 0; i < 12; i++)
+ *data++ = 0 /* MI_NOOP */;
+
+ *data++ = MI_BATCH_BUFFER_END | 1 /* End Context */;
+}
#endif /* GEN10_CONTEXT_H */
diff --git a/src/intel/tools/gen8_context.h b/src/intel/tools/gen8_context.h
index d01c3c87ad8..4b2c83e77fa 100644
--- a/src/intel/tools/gen8_context.h
+++ b/src/intel/tools/gen8_context.h
@@ -24,112 +24,132 @@
#ifndef GEN8_CONTEXT_H
#define GEN8_CONTEXT_H
-static const uint32_t gen8_render_context_init[CONTEXT_RENDER_SIZE / sizeof(uint32_t)] = {
- 0 /* MI_NOOP */,
- MI_LOAD_REGISTER_IMM_n(14) | MI_LRI_FORCE_POSTED,
- 0x2244 /* CONTEXT_CONTROL */, 0x90009 /* Inhibit Synchronous Context Switch | Engine Context Restore Inhibit */,
- 0x2034 /* RING_HEAD */, 0,
- 0x2030 /* RING_TAIL */, 0,
- 0x2038 /* RING_BUFFER_START */, RENDER_RING_ADDR,
- 0x203C /* RING_BUFFER_CONTROL */, (RING_SIZE - 4096) | 1 /* Buffer Length | Ring Buffer Enable */,
- 0x2168 /* BB_HEAD_U */, 0,
- 0x2140 /* BB_HEAD_L */, 0,
- 0x2110 /* BB_STATE */, 0,
- 0x211C /* SECOND_BB_HEAD_U */, 0,
- 0x2114 /* SECOND_BB_HEAD_L */, 0,
- 0x2118 /* SECOND_BB_STATE */, 0,
- 0x21C0 /* BB_PER_CTX_PTR */, 0,
- 0x21C4 /* RCS_INDIRECT_CTX */, 0,
- 0x21C8 /* RCS_INDIRECT_CTX_OFFSET */, 0,
- /* MI_NOOP */
- 0, 0,
-
- 0 /* MI_NOOP */,
- MI_LOAD_REGISTER_IMM_n(9) | MI_LRI_FORCE_POSTED,
- 0x23A8 /* CTX_TIMESTAMP */, 0,
- 0x228C /* PDP3_UDW */, 0,
- 0x2288 /* PDP3_LDW */, 0,
- 0x2284 /* PDP2_UDW */, 0,
- 0x2280 /* PDP2_LDW */, 0,
- 0x227C /* PDP1_UDW */, 0,
- 0x2278 /* PDP1_LDW */, 0,
- 0x2274 /* PDP0_UDW */, PML4_PHYS_ADDR >> 32,
- 0x2270 /* PDP0_LDW */, PML4_PHYS_ADDR,
- /* MI_NOOP */
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-
- 0 /* MI_NOOP */,
- MI_LOAD_REGISTER_IMM_n(1),
- 0x20C8 /* R_PWR_CLK_STATE */, 0x7FFFFFFF,
- MI_BATCH_BUFFER_END
-};
-
-static const uint32_t gen8_blitter_context_init[CONTEXT_OTHER_SIZE / sizeof(uint32_t)] = {
- 0 /* MI_NOOP */,
- MI_LOAD_REGISTER_IMM_n(11) | MI_LRI_FORCE_POSTED,
- 0x22244 /* CONTEXT_CONTROL */, 0x90009 /* Inhibit Synchronous Context Switch | Engine Context Restore Inhibit */,
- 0x22034 /* RING_HEAD */, 0,
- 0x22030 /* RING_TAIL */, 0,
- 0x22038 /* RING_BUFFER_START */, BLITTER_RING_ADDR,
- 0x2203C /* RING_BUFFER_CONTROL */, (RING_SIZE - 4096) | 1 /* Buffer Length | Ring Buffer Enable */,
- 0x22168 /* BB_HEAD_U */, 0,
- 0x22140 /* BB_HEAD_L */, 0,
- 0x22110 /* BB_STATE */, 0,
- 0x2211C /* SECOND_BB_HEAD_U */, 0,
- 0x22114 /* SECOND_BB_HEAD_L */, 0,
- 0x22118 /* SECOND_BB_STATE */, 0,
- /* MI_NOOP */
- 0, 0, 0, 0, 0, 0, 0, 0,
-
- 0 /* MI_NOOP */,
- MI_LOAD_REGISTER_IMM_n(9) | MI_LRI_FORCE_POSTED,
- 0x223A8 /* CTX_TIMESTAMP */, 0,
- 0x2228C /* PDP3_UDW */, 0,
- 0x22288 /* PDP3_LDW */, 0,
- 0x22284 /* PDP2_UDW */, 0,
- 0x22280 /* PDP2_LDW */, 0,
- 0x2227C /* PDP1_UDW */, 0,
- 0x22278 /* PDP1_LDW */, 0,
- 0x22274 /* PDP0_UDW */, PML4_PHYS_ADDR >> 32,
- 0x22270 /* PDP0_LDW */, PML4_PHYS_ADDR,
- /* MI_NOOP */
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-
- MI_BATCH_BUFFER_END
-};
-
-static const uint32_t gen8_video_context_init[CONTEXT_OTHER_SIZE / sizeof(uint32_t)] = {
- 0 /* MI_NOOP */,
- MI_LOAD_REGISTER_IMM_n(11) | MI_LRI_FORCE_POSTED,
- 0x1C244 /* CONTEXT_CONTROL */, 0x90009 /* Inhibit Synchronous Context Switch | Engine Context Restore Inhibit */,
- 0x1C034 /* RING_HEAD */, 0,
- 0x1C030 /* RING_TAIL */, 0,
- 0x1C038 /* RING_BUFFER_START */, VIDEO_RING_ADDR,
- 0x1C03C /* RING_BUFFER_CONTROL */, (RING_SIZE - 4096) | 1 /* Buffer Length | Ring Buffer Enable */,
- 0x1C168 /* BB_HEAD_U */, 0,
- 0x1C140 /* BB_HEAD_L */, 0,
- 0x1C110 /* BB_STATE */, 0,
- 0x1C11C /* SECOND_BB_HEAD_U */, 0,
- 0x1C114 /* SECOND_BB_HEAD_L */, 0,
- 0x1C118 /* SECOND_BB_STATE */, 0,
+static inline void gen8_render_context_init(uint32_t *data, uint32_t *size)
+{
+ *size = CONTEXT_RENDER_SIZE;
+ if (!data)
+ return;
+
+ *data++ = 0 /* MI_NOOP */;
+ MI_LOAD_REGISTER_IMM_vals(data, MI_LRI_FORCE_POSTED,
+ 0x2244 /* CONTEXT_CONTROL */,
+ 0x90009 /* Inhibit Synchronous Context Switch | Engine Context Restore Inhibit */,
+ 0x2034 /* RING_HEAD */, 0,
+ 0x2030 /* RING_TAIL */, 0,
+ 0x2038 /* RING_BUFFER_START */, RENDER_RING_ADDR,
+ 0x203C /* RING_BUFFER_CONTROL */, (RING_SIZE - 4096) | 1 /* Buffer Length | Ring Buffer Enable */,
+ 0x2168 /* BB_HEAD_U */, 0,
+ 0x2140 /* BB_HEAD_L */, 0,
+ 0x2110 /* BB_STATE */, 0,
+ 0x211C /* SECOND_BB_HEAD_U */, 0,
+ 0x2114 /* SECOND_BB_HEAD_L */, 0,
+ 0x2118 /* SECOND_BB_STATE */, 0,
+ 0x21C0 /* BB_PER_CTX_PTR */, 0,
+ 0x21C4 /* RCS_INDIRECT_CTX */, 0,
+ 0x21C8 /* RCS_INDIRECT_CTX_OFFSET */, 0);
/* MI_NOOP */
- 0, 0, 0, 0, 0, 0, 0, 0,
-
- 0 /* MI_NOOP */,
- MI_LOAD_REGISTER_IMM_n(9) | MI_LRI_FORCE_POSTED,
- 0x1C3A8 /* CTX_TIMESTAMP */, 0,
- 0x1C28C /* PDP3_UDW */, 0,
- 0x1C288 /* PDP3_LDW */, 0,
- 0x1C284 /* PDP2_UDW */, 0,
- 0x1C280 /* PDP2_LDW */, 0,
- 0x1C27C /* PDP1_UDW */, 0,
- 0x1C278 /* PDP1_LDW */, 0,
- 0x1C274 /* PDP0_UDW */, PML4_PHYS_ADDR >> 32,
- 0x1C270 /* PDP0_LDW */, PML4_PHYS_ADDR,
+ *data++ = 0;
+ *data++ = 0;
+
+ *data++ = 0; /* MI_NOOP */
+ MI_LOAD_REGISTER_IMM_vals(data, MI_LRI_FORCE_POSTED,
+ 0x23A8 /* CTX_TIMESTAMP */, 0,
+ 0x228C /* PDP3_UDW */, 0,
+ 0x2288 /* PDP3_LDW */, 0,
+ 0x2284 /* PDP2_UDW */, 0,
+ 0x2280 /* PDP2_LDW */, 0,
+ 0x227C /* PDP1_UDW */, 0,
+ 0x2278 /* PDP1_LDW */, 0,
+ 0x2274 /* PDP0_UDW */, PML4_PHYS_ADDR >> 32,
+ 0x2270 /* PDP0_LDW */, PML4_PHYS_ADDR);
/* MI_NOOP */
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ for (int i = 0; i < 12; i++)
+ *data++ = 0 /* MI_NOOP */;
+
+ *data++ = 0 /* MI_NOOP */;
+ MI_LOAD_REGISTER_IMM_vals(data, 0,
+ 0x20C8 /* R_PWR_CLK_STATE */, 0x7FFFFFFF);
+ *data++ = MI_BATCH_BUFFER_END;
+}
+
+static inline void gen8_blitter_context_init(uint32_t *data, uint32_t *size)
+{
+ *size = CONTEXT_OTHER_SIZE;
+ if (!data)
+ return;
+
+ *data++ = 0 /* MI_NOOP */;
+ MI_LOAD_REGISTER_IMM_vals(data, MI_LRI_FORCE_POSTED,
+ 0x22244 /* CONTEXT_CONTROL */, 0x90009 /* Inhibit Synchronous Context Switch | Engine Context Restore Inhibit */,
+ 0x22034 /* RING_HEAD */, 0,
+ 0x22030 /* RING_TAIL */, 0,
+ 0x22038 /* RING_BUFFER_START */, BLITTER_RING_ADDR,
+ 0x2203C /* RING_BUFFER_CONTROL */, (RING_SIZE - 4096) | 1 /* Buffer Length | Ring Buffer Enable */,
+ 0x22168 /* BB_HEAD_U */, 0,
+ 0x22140 /* BB_HEAD_L */, 0,
+ 0x22110 /* BB_STATE */, 0,
+ 0x2211C /* SECOND_BB_HEAD_U */, 0,
+ 0x22114 /* SECOND_BB_HEAD_L */, 0,
+ 0x22118 /* SECOND_BB_STATE */, 0);
+
+ for (int i = 0; i < 8; i++)
+ *data++ = 0 /* MI_NOOP */;
+
+ *data = 0 /* MI_NOOP */;
+ MI_LOAD_REGISTER_IMM_vals(data, MI_LRI_FORCE_POSTED,
+ 0x223A8 /* CTX_TIMESTAMP */, 0,
+ 0x2228C /* PDP3_UDW */, 0,
+ 0x22288 /* PDP3_LDW */, 0,
+ 0x22284 /* PDP2_UDW */, 0,
+ 0x22280 /* PDP2_LDW */, 0,
+ 0x2227C /* PDP1_UDW */, 0,
+ 0x22278 /* PDP1_LDW */, 0,
+ 0x22274 /* PDP0_UDW */, PML4_PHYS_ADDR >> 32,
+ 0x22270 /* PDP0_LDW */, PML4_PHYS_ADDR);
+
+ for (int i = 0; i < 12; i++)
+ *data++ = 0 /* MI_NOOP */;
+
+ *data++ = MI_BATCH_BUFFER_END;
+}
+
+static inline void gen8_video_context_init(uint32_t *data, uint32_t *size)
+{
+ *size = CONTEXT_OTHER_SIZE;
+ if (!data)
+ return;
+
+ *data++ = 0 /* MI_NOOP */;
+ MI_LOAD_REGISTER_IMM_vals(data, MI_LRI_FORCE_POSTED,
+ 0x1C244 /* CONTEXT_CONTROL */, 0x90009 /* Inhibit Synchronous Context Switch | Engine Context Restore Inhibit */,
+ 0x1C034 /* RING_HEAD */, 0,
+ 0x1C030 /* RING_TAIL */, 0,
+ 0x1C038 /* RING_BUFFER_START */, VIDEO_RING_ADDR,
+ 0x1C03C /* RING_BUFFER_CONTROL */, (RING_SIZE - 4096) | 1 /* Buffer Length | Ring Buffer Enable */,
+ 0x1C168 /* BB_HEAD_U */, 0,
+ 0x1C140 /* BB_HEAD_L */, 0,
+ 0x1C110 /* BB_STATE */, 0,
+ 0x1C11C /* SECOND_BB_HEAD_U */, 0,
+ 0x1C114 /* SECOND_BB_HEAD_L */, 0,
+ 0x1C118 /* SECOND_BB_STATE */, 0);
+ for (int i = 0; i < 8; i++)
+ *data++ = 0 /* MI_NOOP */;
+
+ *data++ = 0 /* MI_NOOP */;
+ MI_LOAD_REGISTER_IMM_vals(data, MI_LRI_FORCE_POSTED,
+ 0x1C3A8 /* CTX_TIMESTAMP */, 0,
+ 0x1C28C /* PDP3_UDW */, 0,
+ 0x1C288 /* PDP3_LDW */, 0,
+ 0x1C284 /* PDP2_UDW */, 0,
+ 0x1C280 /* PDP2_LDW */, 0,
+ 0x1C27C /* PDP1_UDW */, 0,
+ 0x1C278 /* PDP1_LDW */, 0,
+ 0x1C274 /* PDP0_UDW */, PML4_PHYS_ADDR >> 32,
+ 0x1C270 /* PDP0_LDW */, PML4_PHYS_ADDR);
+ for (int i = 0; i < 12; i++)
+ *data++ = 0 /* MI_NOOP */;
- MI_BATCH_BUFFER_END
-};
+ *data++ = MI_BATCH_BUFFER_END;
+}
#endif /* GEN8_CONTEXT_H */
diff --git a/src/intel/tools/gen_context.h b/src/intel/tools/gen_context.h
index 3f488c07c9a..e7b75806e4e 100644
--- a/src/intel/tools/gen_context.h
+++ b/src/intel/tools/gen_context.h
@@ -97,6 +97,14 @@
* Valid
*/
+#define MI_LOAD_REGISTER_IMM_vals(data, flags, ...) do { \
+ uint32_t __regs[] = { __VA_ARGS__ }; \
+ assert((ARRAY_SIZE(__regs) % 2) == 0); \
+ *(data)++ = MI_LOAD_REGISTER_IMM_n(ARRAY_SIZE(__regs) / 2) | (flags); \
+ for (unsigned __e = 0; __e < ARRAY_SIZE(__regs); __e++) \
+ *(data)++ = __regs[__e]; \
+ } while (0)
+
#define RENDER_CONTEXT_DESCRIPTOR ((uint64_t)1 << 62 | RENDER_CONTEXT_ADDR | CONTEXT_FLAGS)
#define BLITTER_CONTEXT_DESCRIPTOR ((uint64_t)2 << 62 | BLITTER_CONTEXT_ADDR | CONTEXT_FLAGS)
#define VIDEO_CONTEXT_DESCRIPTOR ((uint64_t)3 << 62 | VIDEO_CONTEXT_ADDR | CONTEXT_FLAGS)
--
2.19.0
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