[Mesa-dev] [PATCH 7/9] i965: Do a WA blit between ASTC main and shadow

[Nanley Chery]

Perform a workaround blit prior to sampling from the ASTC miptree.
---
 src/mesa/drivers/dri/i965/brw_blorp.c | 20 ++++++++++++++++++++
 src/mesa/drivers/dri/i965/brw_blorp.h |  6 ++++++
 src/mesa/drivers/dri/i965/brw_draw.c  | 16 ++++++++++++++++
 3 files changed, 42 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c
index 2ebd35ae49f..6fc0b441cd0 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -266,6 +266,26 @@ swizzle_to_scs(GLenum swizzle)
    return (enum isl_channel_select)((swizzle + 4) & 7);
 }
 
+void
+brw_blorp_copy_astc_wa(struct brw_context *brw,
+                       struct intel_mipmap_tree *src_mt,
+                       struct intel_mipmap_tree *dst_mt,
+                       unsigned level, unsigned layer)
+{
+   struct blorp_surf src_surf, dst_surf;
+   unsigned src_level = level;
+   unsigned dst_level = level;
+   blorp_surf_for_miptree(brw, &src_surf, src_mt, ISL_AUX_USAGE_NONE, false,
+                          &src_level, layer, 1);
+   blorp_surf_for_miptree(brw, &dst_surf, dst_mt, ISL_AUX_USAGE_NONE, true,
+                          &dst_level, layer, 1);
+
+   struct blorp_batch batch;
+   blorp_batch_init(&brw->blorp, &batch, brw, 0);
+   blorp_copy_astc_wa(&batch, &src_surf, &dst_surf, dst_level, layer);
+   blorp_batch_finish(&batch);
+}
+
 /**
  * Note: if the src (or dst) is a 2D multisample array texture on Gen7+ using
  * INTEL_MSAA_LAYOUT_UMS or INTEL_MSAA_LAYOUT_CMS, src_layer (dst_layer) is
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h b/src/mesa/drivers/dri/i965/brw_blorp.h
index 551e1fcdcba..ba0d5679a04 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp.h
@@ -34,6 +34,12 @@ extern "C" {
 
 void brw_blorp_init(struct brw_context *brw);
 
+void
+brw_blorp_copy_astc_wa(struct brw_context *brw,
+                       struct intel_mipmap_tree *src_mt,
+                       struct intel_mipmap_tree *dst_mt,
+                       unsigned level, unsigned layer);
+
 void
 brw_blorp_blit_miptrees(struct brw_context *brw,
                         struct intel_mipmap_tree *src_mt,
diff --git a/src/mesa/drivers/dri/i965/brw_draw.c b/src/mesa/drivers/dri/i965/brw_draw.c
index 8536c040109..772f8f8fad7 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -558,6 +558,22 @@ brw_predraw_resolve_inputs(struct brw_context *brw, bool rendering,
       if (tex_obj->base.StencilSampling ||
           tex_obj->mt->format == MESA_FORMAT_S_UINT8) {
          intel_update_r8stencil(brw, tex_obj->mt);
+      } else if (intel_miptree_has_astc_shadow(tex_obj->mt) &&
+                 tex_obj->mt->shadow_needs_update) {
+         struct intel_mipmap_tree *src = tex_obj->mt;
+         struct intel_mipmap_tree *dst = src->shadow_mt;
+
+         for (int level = src->first_level; level <= src->last_level; level++) {
+            const unsigned depth = src->surf.dim == ISL_SURF_DIM_3D ?
+               minify(src->surf.logical_level0_px.depth, level) :
+               src->surf.logical_level0_px.array_len;
+
+            for (unsigned layer = 0; layer < depth; layer++) {
+               brw_blorp_copy_astc_wa(brw, src, dst, level, layer);
+            }
+         }
+         brw_cache_flush_for_read(brw, dst->bo);
+         src->shadow_needs_update = false;
       }
    }
 
-- 
2.19.0