[Mesa-dev] [PATCH] radeonsi/gfx9: use the correct condition for the DPBB + QUANT_MODE workaround
Marek Olšák
maraeo at gmail.com
Thu Apr 18 02:17:38 UTC 2019
From: Marek Olšák <marek.olsak at amd.com>
---
src/gallium/drivers/radeonsi/si_state_viewport.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/radeonsi/si_state_viewport.c b/src/gallium/drivers/radeonsi/si_state_viewport.c
index 1ec69216841..83905d36ee6 100644
--- a/src/gallium/drivers/radeonsi/si_state_viewport.c
+++ b/src/gallium/drivers/radeonsi/si_state_viewport.c
@@ -359,21 +359,22 @@ static void si_set_viewport_states(struct pipe_context *pctx,
max_extent += distance_off_center;
/* Determine the best quantization mode (subpixel precision),
* but also leave enough space for the guardband.
*
* Note that primitive binning requires QUANT_MODE == 16_8 on Vega10
* and Raven1. What we do depends on the chip:
* - Vega10: Never use primitive binning.
* - Raven1: Always use QUANT_MODE == 16_8.
*/
- if (ctx->family == CHIP_RAVEN)
+ if ((ctx->family == CHIP_VEGA10 || ctx->family == CHIP_RAVEN) &&
+ ctx->screen->dpbb_allowed)
max_extent = 16384; /* Use QUANT_MODE == 16_8. */
/* Another constraint is that all coordinates in the viewport
* are representable in fixed point with respect to the
* surface origin.
*
* It means that PA_SU_HARDWARE_SCREEN_OFFSET can't be given
* an offset that would make the upper corner of the viewport
* greater than the maximum representable number post
* quantization, ie 2^quant_bits.
--
2.17.1
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