[Mesa-dev] [PATCH 2/2] radv/gfx10: add missing dcc_tile_swizzle tweak

[Samuel Pitoiset]

Fixes: c90f46700dd ("radv/gfx10: mask DCC tile swizzle by alignment")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
---
 src/amd/vulkan/radv_image.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index 221b554e73e..8ff93e4344c 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -484,7 +484,9 @@ si_set_mutable_tex_desc_fields(struct radv_device *device,
 			if (chip_class <= GFX8)
 				meta_va += base_level_info->dcc_offset;
 
-			meta_va |= (uint32_t)plane->surface.tile_swizzle << 8;
+			unsigned dcc_tile_swizzle = plane->surface.tile_swizzle << 8;
+			dcc_tile_swizzle &= plane->surface.dcc_alignment - 1;
+			meta_va |= dcc_tile_swizzle;
 		} else if (!is_storage_image &&
 			   radv_image_is_tc_compat_htile(image)) {
 			meta_va = gpu_address + image->htile_offset;
-- 
2.22.0