[Mesa-dev] [PATCH v3 40/44] i965/fs: remove brw_rounding_mode() and use brw_float_controls_mode() instead

[Samuel Iglesias Gonsálvez]

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
---
 src/intel/compiler/brw_eu.h             |  4 ---
 src/intel/compiler/brw_eu_emit.c        | 36 -------------------------
 src/intel/compiler/brw_fs_generator.cpp | 13 +++++++--
 3 files changed, 11 insertions(+), 42 deletions(-)

diff --git a/src/intel/compiler/brw_eu.h b/src/intel/compiler/brw_eu.h
index 2309d3b10d8..ae068964936 100644
--- a/src/intel/compiler/brw_eu.h
+++ b/src/intel/compiler/brw_eu.h
@@ -673,10 +673,6 @@ brw_broadcast(struct brw_codegen *p,
               struct brw_reg src,
               struct brw_reg idx);
 
-void
-brw_rounding_mode(struct brw_codegen *p,
-                  enum brw_rnd_mode mode);
-
 void
 brw_float_controls_mode(struct brw_codegen *p,
                         unsigned mode, unsigned mask);
diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c
index 9de829e85f0..84075155832 100644
--- a/src/intel/compiler/brw_eu_emit.c
+++ b/src/intel/compiler/brw_eu_emit.c
@@ -3665,42 +3665,6 @@ brw_WAIT(struct brw_codegen *p)
    brw_inst_set_mask_control(devinfo, insn, BRW_MASK_DISABLE);
 }
 
-/**
- * Changes the floating point rounding mode updating the control register
- * field defined at cr0.0[5-6] bits. This function supports the changes to
- * RTNE (00), RU (01), RD (10) and RTZ (11) rounding using bitwise operations.
- * Only RTNE and RTZ rounding are enabled at nir.
- */
-void
-brw_rounding_mode(struct brw_codegen *p,
-                  enum brw_rnd_mode mode)
-{
-   const unsigned bits = mode << BRW_CR0_RND_MODE_SHIFT;
-
-   if (bits != BRW_CR0_RND_MODE_MASK) {
-      brw_inst *inst = brw_AND(p, brw_cr0_reg(0), brw_cr0_reg(0),
-                               brw_imm_ud(~BRW_CR0_RND_MODE_MASK));
-      brw_inst_set_exec_size(p->devinfo, inst, BRW_EXECUTE_1);
-
-      /* From the Skylake PRM, Volume 7, page 760:
-       *  "Implementation Restriction on Register Access: When the control
-       *   register is used as an explicit source and/or destination, hardware
-       *   does not ensure execution pipeline coherency. Software must set the
-       *   thread control field to ‘switch’ for an instruction that uses
-       *   control register as an explicit operand."
-       */
-      brw_inst_set_thread_control(p->devinfo, inst, BRW_THREAD_SWITCH);
-    }
-
-   if (bits) {
-      brw_inst *inst = brw_OR(p, brw_cr0_reg(0), brw_cr0_reg(0),
-                              brw_imm_ud(bits));
-      brw_inst_set_exec_size(p->devinfo, inst, BRW_EXECUTE_1);
-      brw_inst_set_thread_control(p->devinfo, inst, BRW_THREAD_SWITCH);
-   }
-}
-
-/* TODO: Refactor brw_rounding_mode() to use this. */
 void
 brw_float_controls_mode(struct brw_codegen *p,
                         unsigned mode, unsigned mask)
diff --git a/src/intel/compiler/brw_fs_generator.cpp b/src/intel/compiler/brw_fs_generator.cpp
index fd6201f2220..418c3fee44d 100644
--- a/src/intel/compiler/brw_fs_generator.cpp
+++ b/src/intel/compiler/brw_fs_generator.cpp
@@ -2435,9 +2435,18 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width)
          brw_DIM(p, dst, retype(src[0], BRW_REGISTER_TYPE_F));
          break;
 
-      case SHADER_OPCODE_RND_MODE:
+      case SHADER_OPCODE_RND_MODE: {
          assert(src[0].file == BRW_IMMEDIATE_VALUE);
-         brw_rounding_mode(p, (enum brw_rnd_mode) src[0].d);
+         /*
+          * Changes the floating point rounding mode updating the control register
+          * field defined at cr0.0[5-6] bits. This function supports the changes to
+          * RTNE (00), RU (01), RD (10) and RTZ (11) rounding using bitwise operations.
+          * Only RTNE and RTZ rounding are enabled at nir.
+          */
+         enum brw_rnd_mode mode =
+            (enum brw_rnd_mode) (src[0].d << BRW_CR0_RND_MODE_SHIFT);
+         brw_float_controls_mode(p, mode, BRW_CR0_RND_MODE_MASK);
+      }
          break;
 
       case SHADER_OPCODE_FLOAT_CONTROL_MODE:
-- 
2.19.1