[Mesa-dev] [PATCH 2/2] radeonsi: fix EXPLICIT_FLUSH for flush offsets > 0

[Marek Olšák]

From: Marek Olšák <marek.olsak at amd.com>

Cc: 18.3 19.0 <mesa-stable at lists.freedesktop.org>
---
 src/gallium/drivers/radeonsi/si_buffer.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_buffer.c b/src/gallium/drivers/radeonsi/si_buffer.c
index bac561de2cb..c01118ce96a 100644
--- a/src/gallium/drivers/radeonsi/si_buffer.c
+++ b/src/gallium/drivers/radeonsi/si_buffer.c
@@ -518,24 +518,27 @@ static void *si_buffer_transfer_map(struct pipe_context *ctx,
 }
 
 static void si_buffer_do_flush_region(struct pipe_context *ctx,
 				      struct pipe_transfer *transfer,
 				      const struct pipe_box *box)
 {
 	struct si_transfer *stransfer = (struct si_transfer*)transfer;
 	struct si_resource *buf = si_resource(transfer->resource);
 
 	if (stransfer->staging) {
+		unsigned src_offset = stransfer->offset +
+				      transfer->box.x % SI_MAP_BUFFER_ALIGNMENT +
+				      (box->x - transfer->box.x);
+
 		/* Copy the staging buffer into the original one. */
 		si_copy_buffer((struct si_context*)ctx, transfer->resource,
-			       &stransfer->staging->b.b, box->x,
-			       stransfer->offset + box->x % SI_MAP_BUFFER_ALIGNMENT,
+			       &stransfer->staging->b.b, box->x, src_offset,
 			       box->width);
 	}
 
 	util_range_add(&buf->valid_buffer_range, box->x,
 		       box->x + box->width);
 }
 
 static void si_buffer_flush_region(struct pipe_context *ctx,
 				   struct pipe_transfer *transfer,
 				   const struct pipe_box *rel_box)
-- 
2.17.1